公开(公告)号：US20140147968A1

公开(公告)日：2014-05-29

申请号：US14168293

申请日：2014-01-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takafumi MIZOGUCHI ,  Kojiro SHIRAISHI

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/41733

Abstract: Provided is a method for manufacturing a semiconductor device so as not expose a semiconductor layer to moisture and the number of masks is reduced. For example, a first conductive film, a first insulating film, a semiconductor film, a second conductive film, and a mask film are formed. The first mask film is processed to form a first mask layer. Dry etching is performed on the first insulating film, the semiconductor film, and the second conductive film with the use of the first mask layer to form a thin film stack body, so that a surface of the first conductive film is at least exposed. Sidewall insulating layers covering side surfaces of the thin film stack body are formed. The first conductive film is side-etched to form a first electrode. A second electrode layer is formed with the second mask layer.

Abstract translation: 提供一种制造半导体器件的方法，以使半导体层不暴露于湿气，并且掩模的数量减少。 例如，形成第一导电膜，第一绝缘膜，半导体膜，第二导电膜和掩模膜。 处理第一掩模膜以形成第一掩模层。 使用第一掩模层对第一绝缘膜，半导体膜和第二导电膜进行干蚀刻，以形成薄膜堆叠体，使得第一导电膜的表面至少露出。 形成覆盖薄膜叠层体的侧面的侧壁绝缘层。 第一导电膜被侧蚀刻以形成第一电极。 第二电极层与第二掩模层形成。

公开(公告)号：US20160336459A1

公开(公告)日：2016-11-17

申请号：US15219764

申请日：2016-07-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takafumi MIZOGUCHI ,  Kojiro SHIRAISHI ,  Masashi TSUBUKU

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L29/78606 ,  H01L21/764 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.

Abstract translation: 本发明的目的是提供一种制造半导体器件的方法，而不会将特定层暴露于湿气等。 制造薄膜元件，使得第一膜，第二膜和第三膜按此顺序堆叠; 在第三膜上形成抗蚀剂掩模; 通过使用抗蚀剂掩模蚀刻第三膜来形成掩模层; 去除抗蚀剂掩模; 通过使用掩模层对第二膜和第一膜进行干蚀刻来形成第二层和第一层; 形成第四膜至少覆盖第二层和第一层; 并且通过在第四膜上进行回蚀而形成侧壁层以至少覆盖第一层的整个侧表面。

公开(公告)号：US20150144949A1

公开(公告)日：2015-05-28

申请号：US14607664

申请日：2015-01-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Takafumi MIZOGUCHI

IPC: H01L29/786

CPC classification number: H01L29/78669 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78678 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device having a stacked structure in which a lower layer is exposed is provided without increasing the number of masks. A source electrode layer and a drain electrode layer are formed by forming a conductive film to have a two-layer structure, forming an etching mask thereover, etching the conductive film using the etching mask, and performing side-etching on an upper layer of the conductive film in a state where the etching mask is left so that part of a lower layer is exposed. The thus formed source and drain electrode layers and a pixel electrode layer are connected in a portion of the exposed lower layer. In the conductive film, the lower layer and the upper layer may be a Ti layer and an Al layer, respectively. The plurality of openings may be provided in the etching mask.

Abstract translation: 提供具有其中暴露下层的层叠结构的半导体器件的制造方法，而不增加掩模的数量。 源极电极层和漏极电极层通过形成具有两层结构的导电膜形成，在其上形成蚀刻掩模，使用蚀刻掩模蚀刻导电膜，并且在上层上进行侧蚀刻 在蚀刻掩模留下的状态下使得下层的一部分露出的导电膜。 这样形成的源极和漏极电极层和像素电极层连接在暴露的下层的一部分中。 在导电膜中，下层和上层可以分别为Ti层和Al层。 多个开口可以设置在蚀刻掩模中。