公开(公告)号：US20170222654A1

公开(公告)日：2017-08-03

申请号：US15407334

申请日：2017-01-17

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Ben Peng XUN ,  Fei LIU ,  Meng Meng GUO ,  Hua TANG ,  Haifeng YANG

IPC分类号： H03M1/12 ,  H03M1/38

CPC分类号： H03M1/125 ,  H03M1/38 ,  H03M1/42 ,  H03M1/44 ,  H03M1/46

摘要： The present disclosure provides asynchronous successive approximation register analog-to-digital convener (ASAR ADC) circuits and signal conversion method thereof. An exemplary ASAR AC circuit includes a sample/hold circuit configured to input a first analog signal and output a second analog signal; a digital-to-analog converter circuit configured to output a third analog signal; a first voltage comparison circuit configured to respond to a valid level of a latch signal, and output a first logic level and a second logic level; a first logic circuit configured to respond to a valid level of a flag signal, and identify a comparison result of the first voltage comparison circuit and output the first digit signal; and a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid levels independently from the first logic level and the second logic level.

公开(公告)号：US20180262203A1

公开(公告)日：2018-09-13

申请号：US15916517

申请日：2018-03-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Hai Feng YANG ,  Hua TANG ,  Fei LIU ,  Ben Peng XUN ,  Xiao Ming ZHU

IPC分类号： H03M1/46 ,  H03M1/06

摘要： A comparator and a successive approximation analog-to-digital converter are provided. The comparator includes a pre-operational amplifier, a latch, a level shift unit, and a reset unit. The pre-operational amplifier receives a to-be-compared signal, and outputs a first-stage amplification signal and a latch clock signal. The latch includes a first inverter circuit and a second inverter circuit, receives and compares the first-stage amplification signal, and outputs a comparison result signal. The level shift unit includes a first level shift circuit and a second level shift circuit, and generates a potential difference between working transistors in the first inverter circuit and the second inverter circuit, respectively. The reset unit includes a first reset circuit and a second reset circuit, and resets a voltage of a node where the level shift unit, the first inverter circuit and the second inverter circuit are coupled when the latch clock signal is at a low level.