-
公开(公告)号:US20220277992A1
公开(公告)日:2022-09-01
申请号:US17744434
申请日:2022-05-13
申请人: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人: Hao ZHANG , Xuezhen JING , Jingjing TAN , Tiantian ZHANG , Zhangru XIAO , Zengsheng XU
IPC分类号: H01L21/768 , H01L23/535
摘要: The semiconductor structure includes a substrate; a dielectric layer formed on the substrate; an opening, formed through the dielectric layer; a contact layer formed at bottom of the opening; a blocking layer formed on a sidewall surface of the opening; and a plug formed in the opening. The plug is formed on a sidewall surface of the blocking layer and in contact with the contact layer.
-
公开(公告)号:US20240258238A1
公开(公告)日:2024-08-01
申请号:US18565406
申请日:2021-05-31
申请人: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人: Zengsheng XU , Xuezhen JING , Hao ZHANG , Tiantian ZHANG , Hailong YU
IPC分类号: H01L23/532 , H01L21/285
CPC分类号: H01L23/53257 , H01L21/28568
摘要: A semiconductor structure includes a substrate, a covering layer on the substrate, an auxiliary layer on the covering layer, a first dielectric layer on surfaces of the substrate and the auxiliary layer, and a conductive structure in the first dielectric layer. The semiconductor structure also includes a second dielectric layer on surfaces of the first dielectric layer and the conductive structure, a first opening in the second dielectric layer and the first dielectric layer, and a second opening in the second dielectric layer. The first opening exposes the auxiliary layer, and the second opening exposes the top surface of the conductive structure. A first conductive layer is in the first opening, and a second conductive layer is in the second opening. A growth rate of the first conductive layer over the auxiliary layer is higher than the growth rate of the first conductive layer over the covering layer.
-
公开(公告)号:US20220077291A1
公开(公告)日:2022-03-10
申请号:US17446017
申请日:2021-08-26
申请人: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人: Hailong YU , Xuezhen JING , Hao ZHANG , Tiantian ZHANG , Jinhui MENG
IPC分类号: H01L29/417 , H01L27/088 , H01L29/06 , H01L21/8234 , H01L21/768
摘要: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The method includes providing a substrate, forming a first dielectric layer and a plurality of gate structures, forming source-drain doped regions, and forming a source-drain plug. The first dielectric layer covers surfaces of the gate structure, the source-drain doped region and the source-drain plug. The method also includes forming a first plug in the first dielectric layer, and forming a second dielectric layer on the first dielectric layer. The first plug is in contact with a top surface of one of the source-drain plug and the gate structure. The second dielectric layer covers the first plug. Further, the method includes forming a second plug material film in the first and second dielectric layers. The second plug material film is in contact with the top surface of one of the source-drain plug and the gate structure.
-
公开(公告)号:US20210043505A1
公开(公告)日:2021-02-11
申请号:US16987556
申请日:2020-08-07
申请人: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人: Hao ZHANG , Xuezhen JING , Jingjing TAN , Tiantian ZHANG , Zhangru XIAO , Zengsheng XU
IPC分类号: H01L21/768 , H01L23/535
摘要: A method for forming a semiconductor structure includes forming a dielectric layer with an opening on a substrate; forming a material film in the opening; forming a blocking film on the material film; and removing the blocking film at the bottom of the opening to expose the material film. The remaining blocking film forms an initial blocking layer. The method further includes forming a conductive-material film in the opening; performing an annealing process to form a contact layer at the bottom of the opening by making the substrate, the material film, and the conductive-material film react with each other; and planarizing the conductive-material film, the initial blocking layer, and the material film to expose the dielectric layer. The remaining initial blocking layer forms a blocking layer in the opening; and the remaining conductive-material film forms a plug in contact with the blocking layer and the contact layer.
-
公开(公告)号:US20210050258A1
公开(公告)日:2021-02-18
申请号:US16989299
申请日:2020-08-10
申请人: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人: Hailong YU , Jingjing TAN , Hao ZHANG
IPC分类号: H01L21/768 , H01L23/532 , H01L23/535
摘要: A method for forming a semiconductor structure includes providing an initial semiconductor structure formed in a substrate; forming a dielectric layer on the substrate; forming a first opening in the dielectric layer to expose a portion of the initial semiconductor structure; etching the portion of the initial semiconductor structure exposed at a bottom of the first opening to form a second opening in the initial semiconductor structure; and forming a contact layer in the second opening and a third opening in the contact layer. The contact layer has a concave top surface, and the third opening is located above the concave top surface of the contact layer and under the first opening. The method further includes forming a conductive structure in the first opening and the third opening.
-
公开(公告)号:US20160064261A1
公开(公告)日:2016-03-03
申请号:US14840587
申请日:2015-08-31
IPC分类号: H01L21/67 , G05B19/418
CPC分类号: G05B19/41865 , G05B2219/32247 , G05B2219/32283 , G05B2219/32313 , G05B2219/45031 , H01L21/67276 , Y02P90/02 , Y02P90/20
摘要: A method of dispatching wafer lots through a plurality of process chambers, wherein the process chambers are disposed in at least one machine. The method includes: receiving wafer lot information and process chamber data, wherein the wafer lot information identifies the wafer lots to be processed at the machine, and the process chamber data includes process information associated with the process chambers; determining a load factor of each process chamber based on the wafer lot information and process chamber data; receiving historical data of run lots previously processed through the process chambers, and determining a processing time of the wafer lots based on the historical data; generating a dispatching criteria for the wafer lots based on the load factors of the process chambers and the determined processing time of the wafer lots; and dispatching the wafer lots through the process chambers based on the dispatching criteria.
摘要翻译: 一种通过多个处理室调度晶片批次的方法,其中处理室设置在至少一个机器中。 该方法包括:接收晶片批信息和处理室数据,其中晶片批信息识别在机器处要处理的晶片批次,并且处理室数据包括与处理室相关联的处理信息; 基于晶片批次信息和处理室数据确定每个处理室的负载系数; 接收先前通过处理室处理的运行批次的历史数据,以及基于历史数据确定晶片批次的处理时间; 基于处理室的负载系数和所确定的晶片批次的处理时间来生成晶片批次的调度标准; 并根据调度标准将晶片批次分配到处理室。
-
-
-
-
-