公开(公告)号：US20210183706A1

公开(公告)日：2021-06-17

申请号：US16861823

申请日：2020-04-29

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Zhuofan CHEN ,  Haiyang ZHANG

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/768

摘要： The present disclosure provides a semiconductor structure and a forming method thereof. The forming method includes forming sacrificial layers and spacer on a dielectric layer, wherein the sacrificial layers and the spacer cover the dielectric layer at the top of a gate and expose the dielectric layer on at least part of source-drain doping layers, the sacrificial layers include the first sacrificial layer located on the dielectric layer at the top of the gate, and side walls of the first sacrificial layer are provided with the spacer; after the sacrificial layers and the spacer is formed, the first sacrificial layer is removed; and the dielectric layer is etched with a patterning layer as a mask, and a first contact hole and second contact holes are formed in the dielectric layer. The embodiments and implementations of the present disclosure can avoid double graphics of the dielectric layer and the alignment error.

公开(公告)号：US20180108667A1

公开(公告)日：2018-04-19

申请号：US15786316

申请日：2017-10-17

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Rongyao CHANG ,  Zhuofan CHEN ,  Haiyang ZHANG

IPC分类号： H01L27/11526 ,  H01L27/11546 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11551

CPC分类号： H01L27/11526 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A flash memory device and its manufacturing method, which is related to semiconductor techniques. The flash memory device comprises: a substrate; and a memory unit on the substrate, comprising: a channel structure on the substrate, wherein the channel structure comprise, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure, wherein there exist cavities between neighboring gate structures; a support structure supporting the gate structures; and a plurality of gate contact components each contacting a gate structure. The cavities between neighboring gate structures lower the parasitic capacitance, reduce inter-gate interference, and suppress the influence from writing or erasing operations of nearby memory units.

公开(公告)号：US20180122855A1

公开(公告)日：2018-05-03

申请号：US15799915

申请日：2017-10-31

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Zhuofan CHEN ,  Yibin SONG ,  Haiyang ZHANG

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/12

CPC分类号： H01L27/222 ,  H01L21/8221 ,  H01L27/0688 ,  H01L43/08 ,  H01L43/12

摘要： A magnetic random access memory and its manufacturing method related to semiconductor techniques. The magnetic random access memory comprises a word line, a bit line, and a memory unit positioned between the word line and the bit line, wherein the memory unit comprises a fixture layer connecting the bit line, a free layer connecting the word line, and an insulation layer positioned between the fixture layer and the free layer. This magnetic random access memory has a simpler design than conventional devices and can be manufactured more easily, which improves the integrity of the manufacturing process.