公开(公告)号：US20210028007A1

公开(公告)日：2021-01-28

申请号：US16935561

申请日：2020-07-22

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Shiliang JI ,  Bo SU ,  Haiyang ZHANG

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L21/3213

摘要： A method for forming a semiconductor structure includes providing a substrate; forming a gate structure on the substrate, the gate structure extending along a first direction; removing a portion of the gate structure to form a trench in the gate structure, the trench penetrating through the gate structure along a second direction which is different form the first direction; performing a first cleaning treatment process on the trench to remove non-metal residues; and performing a second cleaning treatment process on the trench to remove metal residues.

公开(公告)号：US20200273980A1

公开(公告)日：2020-08-27

申请号：US16795864

申请日：2020-02-20

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Haiyang ZHANG ,  Bo SU

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/3065

摘要： The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate having fins and forming an initial gate structure across the fins, which covers a portion of a top surface and sidewall surfaces of the fins, and includes an initial first region and an initial second region on the initial first region. A bottom boundary of the initial second region is higher than the top surface of the fins, and a size of the initial first region is larger than a size of the initial second region. A first etching process is performed on sidewalls of the initial gate structure to form a gate structure, which includes a first region formed by etching the initial first region, and a second region formed by etching the initial second region. A size of the first region is smaller than a size of the second region.

公开(公告)号：US20180122855A1

公开(公告)日：2018-05-03

申请号：US15799915

申请日：2017-10-31

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Zhuofan CHEN ,  Yibin SONG ,  Haiyang ZHANG

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/12

CPC分类号： H01L27/222 ,  H01L21/8221 ,  H01L27/0688 ,  H01L43/08 ,  H01L43/12

摘要： A magnetic random access memory and its manufacturing method related to semiconductor techniques. The magnetic random access memory comprises a word line, a bit line, and a memory unit positioned between the word line and the bit line, wherein the memory unit comprises a fixture layer connecting the bit line, a free layer connecting the word line, and an insulation layer positioned between the fixture layer and the free layer. This magnetic random access memory has a simpler design than conventional devices and can be manufactured more easily, which improves the integrity of the manufacturing process.

公开(公告)号：US20230154848A1

公开(公告)日：2023-05-18

申请号：US18093497

申请日：2023-01-05

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Haiyang ZHANG ,  Panpan LIU

IPC分类号： H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5286 ,  H01L23/53257 ,  H01L23/53228 ,  H01L23/53276

摘要： A semiconductor structure is provided in the present disclosure. The semiconductor structure includes a substrate, a plurality of fins on the substrate, a plurality of isolation structures on the substrate, each formed on a top surface of the substrate between adjacent fins, and a power rail formed in at least one isolation structure of the plurality of isolation structures and further in the substrate, where a top surface of the power rail is lower than a top surface of the plurality of fins.

公开(公告)号：US20210358912A1

公开(公告)日：2021-11-18

申请号：US17322472

申请日：2021-05-17

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Shuaijie CHI ,  Haiyang ZHANG ,  Ermin CHONG ,  Wei TIAN

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234

摘要： Semiconductor structures and fabrication methods thereof are provided. The semiconductor includes a substrate; a gate structure on the substrate; and a dielectric layer on the substrate and covering sidewall surfaces of the gate structure. The dielectric layer includes an opening passing through the gate structure along a direction perpendicular to an extending direction of the gate structure. The semiconductor structure also includes a first isolation layer in the opening and with a top surface lower than a top surface of the gate structure.

公开(公告)号：US20210183706A1

公开(公告)日：2021-06-17

申请号：US16861823

申请日：2020-04-29

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Zhuofan CHEN ,  Haiyang ZHANG

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/768

摘要： The present disclosure provides a semiconductor structure and a forming method thereof. The forming method includes forming sacrificial layers and spacer on a dielectric layer, wherein the sacrificial layers and the spacer cover the dielectric layer at the top of a gate and expose the dielectric layer on at least part of source-drain doping layers, the sacrificial layers include the first sacrificial layer located on the dielectric layer at the top of the gate, and side walls of the first sacrificial layer are provided with the spacer; after the sacrificial layers and the spacer is formed, the first sacrificial layer is removed; and the dielectric layer is etched with a patterning layer as a mask, and a first contact hole and second contact holes are formed in the dielectric layer. The embodiments and implementations of the present disclosure can avoid double graphics of the dielectric layer and the alignment error.

公开(公告)号：US20180261687A1

公开(公告)日：2018-09-13

申请号：US15919375

申请日：2018-03-13

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Panpan LIU ,  Haiyang ZHANG

IPC分类号： H01L29/66 ,  H01L21/822 ,  H01L21/02 ,  H01L27/06 ,  H01L27/12 ,  H01L27/11524 ,  G11C16/04

CPC分类号： H01L29/66787 ,  G11C16/0483 ,  H01L21/02244 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/1211

摘要： A 3-D flash memory device and its manufacturing method, relating to semiconductor technology. The manufacturing method comprises: providing a semiconductor structure comprising a substrate, a first insulation layer on the substrate, a fin structure comprising a first gate layer and a second insulation layer stacked alternately over each other on the first insulation layer, a third insulation layer on two sides of the fin structure, with the first gate layer being surrounded by the first, the second and the third insulation layers, and at least one channel layer covering the fin structure and the third insulation layer; and forming a groove by etching the channel layer, the second insulation layer and the first gate layer along an extension direction of the fin structure. This inventive concept improves the storage density of a 3-D flash memory device.

公开(公告)号：US20180108667A1

公开(公告)日：2018-04-19

申请号：US15786316

申请日：2017-10-17

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Rongyao CHANG ,  Zhuofan CHEN ,  Haiyang ZHANG

IPC分类号： H01L27/11526 ,  H01L27/11546 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11551

CPC分类号： H01L27/11526 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A flash memory device and its manufacturing method, which is related to semiconductor techniques. The flash memory device comprises: a substrate; and a memory unit on the substrate, comprising: a channel structure on the substrate, wherein the channel structure comprise, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure, wherein there exist cavities between neighboring gate structures; a support structure supporting the gate structures; and a plurality of gate contact components each contacting a gate structure. The cavities between neighboring gate structures lower the parasitic capacitance, reduce inter-gate interference, and suppress the influence from writing or erasing operations of nearby memory units.

公开(公告)号：US20240313078A1

公开(公告)日：2024-09-19

申请号：US18681224

申请日：2021-08-05

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Bo SU ,  Hanzhu WU ,  Abraham YOO ,  Haiyang ZHANG

IPC分类号： H01L29/423 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor structure and its fabrication method. First sacrificial layers are formed on a base substrate. Channel structures are formed on the first sacrificial layers. Each channel structure includes stacked channel stack layer(s). Each channel stack layer includes a second sacrificial layer and a channel layer. Dummy gate structures crossing the channel structures are also formed on the base substrate. Etching resistance of the first sacrificial layers is smaller than etching resistance of the second sacrificial layers. The channel structures and the first sacrificial layers on two sides of each dummy gate structure are removed to form first grooves. The first sacrificial layers at the bottoms of the channel structures are removed to form second grooves connected to the first grooves. Isolation layers are formed in the second grooves; and source-drain doping layers are formed in the first grooves.

公开(公告)号：US20230411398A1

公开(公告)日：2023-12-21

申请号：US18038066

申请日：2020-11-24

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Haiyang ZHANG ,  Bo SU ,  Xingyu XIAO

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L27/1207 ,  H01L21/84 ,  H01L21/8221

摘要： Semiconductor structure and formation method are provided. A method of forming a semiconductor structure includes providing a dielectric layer on a substrate, the dielectric layer including a first region and a second region under the first region, the first region including discrete first initial nanowires, and the second region including discrete second initial nanowires; etching the dielectric layer and the first initial nanowires in the first region to form a first opening in the first region, and forming first nanowires from the first initial nanowires; etching the dielectric layer at a bottom of the first opening and the second initial nanowires to form a second opening in the second region, and forming second nanowires from the second initial nanowires; forming a second source/drain layer in the second opening; forming an isolation layer on the second source/drain layer; and forming a first source/drain layer in the first opening.