LOW-POWER RELAXATION OSCILLATOR AND RFID TAG USING THE SAME
    2.
    发明申请
    LOW-POWER RELAXATION OSCILLATOR AND RFID TAG USING THE SAME 审中-公开
    低功耗松弛振荡器和使用该功能的RFID标签

    公开(公告)号:US20100141348A1

    公开(公告)日:2010-06-10

    申请号:US12565240

    申请日:2009-09-23

    IPC分类号: H03K3/023

    CPC分类号: H03K3/03 H03K3/0231

    摘要: There is provided a low-power relaxation oscillator. The low-power relaxation oscillator may include: a constant current generation unit generating a current having a predetermined magnitude; a current varying unit controlling the current generated from the constant current generation unit according to a clock control signal to output the controlled current; a first controller and a second controller connected in parallel with output terminals of the current varying unit and passing or interrupting the current supplied from the current varying unit; a PMOS charging/discharging unit arranged between an output terminal of the first controller and an output terminal of the second controller; a first comparator and a second comparator connected to both ends of the PMOS charging/discharging unit, respectively, and each outputting a high or low level voltage upon receiving voltage charged in the PMOS charging/discharging unit; and a latch circuit delaying the voltages output from the first and second comparators to output oscillation signals.

    摘要翻译: 提供了一个低功耗松弛振荡器。 低功率张弛振荡器可以包括:产生具有预定大小的电流的恒定电流产生单元; 电流变化单元,根据时钟控制信号控制从恒定电流产生单元产生的电流,以输出受控电流; 第一控制器和第二控制器,与电流变化单元的输出端并联连接,并通过或中断从电流变化单元提供的电流; PMOS充电/放电单元,布置在第一控制器的输出端和第二控制器的输出端之间; 分别连接到PMOS充电/放电单元的两端的第一比较器和第二比较器,并且在接收到PMOS充电/放电单元中充电的电压时,分别输出高电平或低电平电压; 以及将从第一和第二比较器输出的电压延迟以输出振荡信号的锁存电路。

    SYSTEM AND METHOD FOR WAFER-LEVEL ADJUSTMENT OF INTEGRATED CIRCUIT CHIPS
    4.
    发明申请
    SYSTEM AND METHOD FOR WAFER-LEVEL ADJUSTMENT OF INTEGRATED CIRCUIT CHIPS 审中-公开
    用于集成电路卡的水平调整的系统和方法

    公开(公告)号:US20100125761A1

    公开(公告)日:2010-05-20

    申请号:US12465579

    申请日:2009-05-13

    IPC分类号: G06F11/00

    CPC分类号: G01R31/318511 G06K19/0722

    摘要: A system and method for wafer level adjusting of IC chips are disclosed. The system and method for a wafer level adjustment of IC chips connect the analog circuits of the IC chip with the adjustment controller outside the semiconductor wafer via the probing region and the signal transmission region outside the IC chip, measure and adjust the performance of the IC chip by the adjustment controller, and then, only store final adjustment data in the adjustment memory of the IC chip. Accordingly, it is possible to reduce the area of adjustment circuits added to an integrated circuit chip such as an RFID tag chip and adjust the performance of chips at a wafer level.

    摘要翻译: 公开了一种用于晶片级调整IC芯片的系统和方法。 IC芯片的晶片级调整的系统和方法通过IC芯片外的探测区域和信号传输区域将IC芯片的模拟电路与半导体晶片外部的调节控制器连接,测量和调整IC的性能 芯片由调节控制器,然后只存储最终调整数据在IC芯片的调整存储器中。 因此,可以减少添加到诸如RFID标签芯片的集成电路芯片的调整电路的面积,并且在晶片级调整芯片的性能。