SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION
    2.
    发明申请
    SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION 审中-公开
    改变噪声减少的不活动时钟边缘

    公开(公告)号:US20090102529A1

    公开(公告)日:2009-04-23

    申请号:US11876871

    申请日:2007-10-23

    IPC分类号: H03K3/017

    CPC分类号: H03K3/84 H03K7/08

    摘要: An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: multiple clocked elements; a clock signal source providing clock signals to the multiple clocked elements; and a clock shifting means coupled between the clock signal source and each of the multiple clocked elements; wherein the clock shifting means shifts clock signals of the multiple clocked elements such that the clock signals of the multiple clocked elements have aligned active edges and misaligned inactive edges to reduce the clock noise generated by the inactive edges of the clock signals.

    摘要翻译: 公开了集成电路和设计结构。 集成电路可以包括:多个时钟元件; 时钟信号源,向多个时钟元件提供时钟信号; 以及时钟移位装置,其耦合在所述时钟信号源与所述多个时钟元件中的每一个之间; 其中所述时钟移位装置移动所述多个时钟元件的时钟信号,使得所述多个时钟元件的时钟信号具有对准的有源边沿和未对准的非有效边沿,以减少由所述时钟信号的不活动边缘产生的时钟噪声。

    SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION
    3.
    发明申请
    SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION 审中-公开
    改变噪声减少的不活动时钟边缘

    公开(公告)号:US20080046772A1

    公开(公告)日:2008-02-21

    申请号:US11457916

    申请日:2006-07-17

    IPC分类号: G06F1/00

    CPC分类号: G06F1/10

    摘要: A method and system for reducing clock noises are disclosed. A clock signal includes active edges and inactive edges. Inactive edges produce clock noise but are not critical to the functionality of the clock signal. That is, only active edges are critical to proper timing of an integrated circuit (IC). As such, inactive edges of clock signals to clocked elements of an IC may be shifted to be misaligned to one another. As a consequence, peak noise produced by the inactive edges will be spread over a large area and therefore will be reduced in amplitude.

    摘要翻译: 公开了一种减少时钟噪声的方法和系统。 时钟信号包括有效边沿和非活动边沿。 无效边沿产生时钟噪声,但并不对时钟信号的功能至关重要。 也就是说,只有有效边沿对于集成电路(IC)的正确定时至关重要。 因此,到IC的时钟元件的时钟信号的无效边沿可能被移位以彼此不对准。 结果,由无源边缘产生的峰值噪声将在大面积上扩展,因此幅度将被减小。