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公开(公告)号：US20100255633A1
公开(公告)日：2010-10-07
申请号：US12820024
申请日：2010-06-21
申请人： Seung-Hwan CHO , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Min-Ho Yoon , Jung-Hun Noh
发明人： Seung-Hwan CHO , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Min-Ho Yoon , Jung-Hun Noh
IPC分类号： H01L51/40
CPC分类号： H01L51/0541 , H01L51/0023 , H01L51/102
摘要： A manufacturing method for a thin film transistor array panel including forming a gate electrode, forming an insulating layer on the gate electrode, sequentially forming a lower conducting layer and a upper conducting layer on the insulating layer, etching the upper conducting layer to form a first source electrode and a first drain electrode, etching the lower conducting layer to form the second source electrode and the second drain electrode, over-etching the second source electrode and the second drain electrode, and forming an organic semiconductor between the second source electrode and the second drain electrode.
摘要翻译： 一种薄膜晶体管阵列板的制造方法，包括形成栅电极，在栅电极上形成绝缘层，在绝缘层上依次形成下导电层和上导电层，蚀刻上导电层以形成第一 源电极和第一漏电极，蚀刻下导电层以形成第二源电极和第二漏电极，过蚀刻第二源电极和第二漏电极，以及在第二源电极和第二漏电极之间形成有机半导体 第二漏电极。
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公开(公告)号：US07977144B2
公开(公告)日：2011-07-12
申请号：US12772845
申请日：2010-05-03
申请人： Seung-Hwan Cho , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Jung-Hun Noh
发明人： Seung-Hwan Cho , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Jung-Hun Noh
IPC分类号： H01L21/00
CPC分类号： H01L51/0545 , H01L27/283 , H01L27/3244 , H01L51/0021
摘要： A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer insulating layer covering the data line and the drain electrode on the gate insulating layer, forming a first opening in the interlayer insulating layer, forming an organic semiconductor in the first opening, forming a passivation layer on the organic semiconductor and the interlayer insulating layer, and forming a second opening in the interlayer insulating layer to expose the pixel electrode.
摘要翻译： 一种薄膜晶体管阵列面板的制造方法，在基板上形成栅极线和像素电极，形成覆盖栅极线的栅极绝缘层，在栅极绝缘层上形成包括源电极和漏极的数据线， 在所述栅绝缘层上形成覆盖所述数据线和所述漏电极的层间绝缘层，在所述层间绝缘层中形成第一开口，在所述第一开口中形成有机半导体，在所述有机半导体上形成钝化层， 并且在所述层间绝缘层中形成第二开口以使所述像素电极露出。
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公开(公告)号：US20080078993A1
公开(公告)日：2008-04-03
申请号：US11864581
申请日：2007-09-28
申请人： Seung-Hwan CHO , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Min-Ho Yoon , Jung-Hun Noh
发明人： Seung-Hwan CHO , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Min-Ho Yoon , Jung-Hun Noh
CPC分类号： H01L51/0541 , H01L51/0023 , H01L51/102
摘要： A manufacturing method for a thin film transistor array panel including forming a gate electrode, forming an insulating layer on the gate electrode, sequentially forming a lower conducting layer and a upper conducting layer on the insulating layer, etching the upper conducting layer to form a first source electrode and a first drain electrode, etching the lower conducting layer to form the second source electrode and the second drain electrode, over-etching the second source electrode and the second drain electrode, and forming an organic semiconductor between the second source electrode and the second drain electrode.
摘要翻译： 一种薄膜晶体管阵列板的制造方法，包括形成栅电极，在栅电极上形成绝缘层，在绝缘层上依次形成下导电层和上导电层，蚀刻上导电层以形成第一 源电极和第一漏电极，蚀刻下导电层以形成第二源电极和第二漏电极，过蚀刻第二源电极和第二漏电极，以及在第二源电极和第二漏电极之间形成有机半导体 第二漏电极。
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公开(公告)号：US07768000B2
公开(公告)日：2010-08-03
申请号：US11864581
申请日：2007-09-28
申请人： Seung-Hwan Cho , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Min-Ho Yoon , Jung-Hun Noh
发明人： Seung-Hwan Cho , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Min-Ho Yoon , Jung-Hun Noh
CPC分类号： H01L51/0541 , H01L51/0023 , H01L51/102
摘要： A manufacturing method for a thin film transistor array panel including forming a gate electrode, forming an insulating layer on the gate electrode, sequentially forming a lower conducting layer and a upper conducting layer on the insulating layer, etching the upper conducting layer to form a first source electrode and a first drain electrode, etching the lower conducting layer to form the second source electrode and the second drain electrode, over-etching the second source electrode and the second drain electrode, and forming an organic semiconductor between the second source electrode and the second drain electrode.
摘要翻译： 一种薄膜晶体管阵列板的制造方法，包括形成栅电极，在栅电极上形成绝缘层，在绝缘层上依次形成下导电层和上导电层，蚀刻上导电层以形成第一 源电极和第一漏电极，蚀刻下导电层以形成第二源电极和第二漏电极，过蚀刻第二源电极和第二漏电极，以及在第二源电极和第二漏电极之间形成有机半导体 第二漏电极。
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公开(公告)号：US07737448B2
公开(公告)日：2010-06-15
申请号：US11927377
申请日：2007-10-29
申请人： Seung-Hwan Cho , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Jung-Hun Noh
发明人： Seung-Hwan Cho , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Jung-Hun Noh
IPC分类号： H01L27/14
CPC分类号： H01L51/0545 , H01L27/283 , H01L27/3244 , H01L51/0021
摘要： A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer insulating layer covering the data line and the drain electrode on the gate insulating layer, forming a first opening in the interlayer insulating layer, forming an organic semiconductor in the first opening, forming a passivation layer on the organic semiconductor and the interlayer insulating layer, and forming a second opening in the interlayer insulating layer to expose the pixel electrode.
摘要翻译： 一种薄膜晶体管阵列面板的制造方法，在基板上形成栅极线和像素电极，形成覆盖栅极线的栅极绝缘层，在栅极绝缘层上形成包括源电极和漏极的数据线， 在所述栅绝缘层上形成覆盖所述数据线和所述漏电极的层间绝缘层，在所述层间绝缘层中形成第一开口，在所述第一开口中形成有机半导体，在所述有机半导体上形成钝化层， 并且在所述层间绝缘层中形成第二开口以使所述像素电极露出。
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公开(公告)号：US20080237582A1
公开(公告)日：2008-10-02
申请号：US11927377
申请日：2007-10-29
申请人： Seung-Hwan Cho , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Jung-Hun Noh
发明人： Seung-Hwan Cho , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Jung-Hun Noh
CPC分类号： H01L51/0545 , H01L27/283 , H01L27/3244 , H01L51/0021
摘要： A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer insulating layer covering the data line and the drain electrode on the gate insulating layer, forming a first opening in the interlayer insulating layer, forming an organic semiconductor in the first opening, forming a passivation layer on the organic semiconductor and the interlayer insulating layer, and forming a second opening in the interlayer insulating layer to expose the pixel electrode.
摘要翻译： 一种薄膜晶体管阵列面板的制造方法，在基板上形成栅极线和像素电极，形成覆盖栅极线的栅极绝缘层，在栅极绝缘层上形成包括源电极和漏极的数据线， 在所述栅绝缘层上形成覆盖所述数据线和所述漏电极的层间绝缘层，在所述层间绝缘层中形成第一开口，在所述第一开口中形成有机半导体，在所述有机半导体上形成钝化层， 并且在所述层间绝缘层中形成第二开口以使所述像素电极露出。
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公开(公告)号：US08252626B2
公开(公告)日：2012-08-28
申请号：US12820024
申请日：2010-06-21
申请人： Seung-Hwan Cho , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Min-Ho Yoon , Jung-Hun Noh
发明人： Seung-Hwan Cho , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Min-Ho Yoon , Jung-Hun Noh
IPC分类号： H01L51/40
CPC分类号： H01L51/0541 , H01L51/0023 , H01L51/102
摘要： A manufacturing method for a thin film transistor array panel including forming a gate electrode, forming an insulating layer on the gate electrode, sequentially forming a lower conducting layer and a upper conducting layer on the insulating layer, etching the upper conducting layer to form a first source electrode and a first drain electrode, etching the lower conducting layer to form the second source electrode and the second drain electrode, over-etching the second source electrode and the second drain electrode, and forming an organic semiconductor between the second source electrode and the second drain electrode.
摘要翻译： 一种薄膜晶体管阵列板的制造方法，包括形成栅电极，在栅电极上形成绝缘层，在绝缘层上依次形成下导电层和上导电层，蚀刻上导电层以形成第一 源电极和第一漏电极，蚀刻下导电层以形成第二源电极和第二漏电极，过蚀刻第二源电极和第二漏电极，以及在第二源电极和第二漏电极之间形成有机半导体 第二漏电极。
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公开(公告)号：US20100216267A1
公开(公告)日：2010-08-26
申请号：US12772845
申请日：2010-05-03
申请人： Seung-Hwan CHO , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Jung-Hun Noh
发明人： Seung-Hwan CHO , Bo-Sung Kim , Keun-Kyu Song , Tae-Young Choi , Jung-Hun Noh
IPC分类号： H01L51/40
CPC分类号： H01L51/0545 , H01L27/283 , H01L27/3244 , H01L51/0021
摘要： A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer insulating layer covering the data line and the drain electrode on the gate insulating layer, forming a first opening in the interlayer insulating layer, forming an organic semiconductor in the first opening, forming a passivation layer on the organic semiconductor and the interlayer insulating layer, and forming a second opening in the interlayer insulating layer to expose the pixel electrode.
摘要翻译： 一种薄膜晶体管阵列面板的制造方法，在基板上形成栅极线和像素电极，形成覆盖栅极线的栅极绝缘层，在栅极绝缘层上形成包括源电极和漏极的数据线， 在所述栅绝缘层上形成覆盖所述数据线和所述漏电极的层间绝缘层，在所述层间绝缘层中形成第一开口，在所述第一开口中形成有机半导体，在所述有机半导体上形成钝化层， 并且在所述层间绝缘层中形成第二开口以使所述像素电极露出。
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公开(公告)号：US20080296566A1
公开(公告)日：2008-12-04
申请号：US12156213
申请日：2008-05-30
申请人： Keun-Kyu Song , Jung-Han Shin , Bo-Sung Kim , Seon-Pil Jang , Seung-Hwan Cho , Min-Ho Yoon , Jung-Hun Noh
发明人： Keun-Kyu Song , Jung-Han Shin , Bo-Sung Kim , Seon-Pil Jang , Seung-Hwan Cho , Min-Ho Yoon , Jung-Hun Noh
CPC分类号： H01L51/0545 , H01L51/0558
摘要： An organic thin film transistor substrate for a display device includes a gate line, a data line insulated from the gate line, at least two organic thin film transistors, each of which is connected between the gate line and the data line, and both of which are commonly connected to a main drain electrode, and a pixel electrode connected to the main drain electrode.
摘要翻译： 用于显示装置的有机薄膜晶体管基板包括栅极线，与栅极线绝缘的数据线，至少两个有机薄膜晶体管，每个有源薄膜晶体管连接在栅极线和数据线之间， 通常连接到主漏电极和连接到主漏电极的像素电极。
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10.发明申请Organic thin film transistor array panel and method for manufacturing the same 审中-公开有机薄膜晶体管阵列面板及其制造方法公开(公告)号：US20090026445A1
公开(公告)日：2009-01-29
申请号：US12148908
申请日：2008-04-22
申请人： Jung-Hun Noh , Keun-Kyu Song , Seung-Hwan Cho
发明人： Jung-Hun Noh , Keun-Kyu Song , Seung-Hwan Cho
CPC分类号： H01L51/0541 , H01L27/3274 , H01L51/0558
摘要： A method for manufacturing an organic thin film transistor array panel includes forming a data line including a source electrode and a drain electrode apart from the data line on a substrate and forming a bank insulating layer including a first opening and a second opening on the data line and the drain electrode. An organic semiconductor is formed in the first opening, sequential deposition is performed of an insulating material layer and a metal layer on the bank insulating layer and the organic semiconductor. A first passivation layer is formed on the metal layer which is etched using the first passivation layer as an etch mask to form a gate line including a gate electrode. The insulating material layer is etched using the first passivation layer as an etch mask to form a gate insulating layer. A second passivation layer is formed on the first passivation layer and a pixel electrode is formed on the second passivation layer.
摘要翻译： 一种制造有机薄膜晶体管阵列面板的方法包括在基板上形成包括源极电极和漏电极的数据线，该数据线与数据线分开，并在数据线上形成包括第一开口和第二开口的堤绝缘层 和漏电极。 在第一开口中形成有机半导体，在堤绝缘层和有机半导体上进行绝缘材料层和金属层的顺序沉积。 在金属层上形成第一钝化层，使用第一钝化层作为蚀刻掩模进行蚀刻，以形成包括栅电极的栅极线。 使用第一钝化层作为蚀刻掩模蚀刻绝缘材料层以形成栅极绝缘层。 在第一钝化层上形成第二钝化层，在第二钝化层上形成像素电极。
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