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1.发明授权Computer processor utilizing logarithmic conversion and method of use thereof 失效利用对数转换的计算机处理器及其使用方法
公开(公告)号：US5696986A
公开(公告)日：1997-12-09
申请号：US512849
申请日：1995-08-09
CPC分类号： G06F7/48 , G06F1/0307 , G06F7/5235
摘要： A computer processor for performing mathematical operations includes a logarithm converter which generates log values on a data bus, a plurality of processing elements connected to the data bus, an inverse-logarithm converter which receives values from the processing elements, an accumulator which sums converted values from the inverse-logarithm converter, and a control unit for configuring the accumulator to perform various summing operations. The computer processor also includes a switch for providing processor outputs as feedback. An instruction, selected from a set of instructions, is decoded by the control unit to configure the computer processor to perform operations on a data stream.
摘要翻译： 用于执行数学运算的计算机处理器包括对数转换器，其在数据总线上生成对数值，连接到数据总线的多个处理元件，从对该处理元件接收值的反对数转换器，将转换值相加的累加器 以及用于配置所述累加器以执行各种求和操作的控制单元。 计算机处理器还包括用于提供处理器输出作为反馈的开关。 由一组指令选择的指令由控制单元解码以配置计算机处理器对数据流执行操作。
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2.发明授权Computer Processor utilizing logarithmic conversion and method of use thereof 失效利用对数转换的计算机处理器及其使用方法
公开(公告)号：US5685008A
公开(公告)日：1997-11-04
申请号：US403158
申请日：1995-03-13
申请人： Shao Wei Pan , Shay-Ping Thomas Wang , Scott Edward Lloyd , Nicholas Mikulas Labun , David Alan Hayner
发明人： Shao Wei Pan , Shay-Ping Thomas Wang , Scott Edward Lloyd , Nicholas Mikulas Labun , David Alan Hayner
CPC分类号： G06F7/48 , G06F1/0307 , G06F7/5235
摘要： A computer processor for performing mathematical operations includes a logarithm converter which generates log values on a data bus, a plurality of processing elements connected to the data bus, an inverse-logarithm converter which receives values from the processing elements, an accumulator which sums converted values from the inverse-logarithm converter, and a control unit for configuring the accumulator to perform various summing operations. The computer processor also includes a switch for providing processor outputs as feedback. An instruction, selected from a set of instructions, is decoded by the control unit to configure the computer processor to perform operations on a data stream.
摘要翻译： 用于执行数学运算的计算机处理器包括对数转换器，其在数据总线上生成对数值，连接到数据总线的多个处理元件，从对该处理元件接收值的反对数转换器，将转换值相加的累加器 以及用于配置所述累加器以执行各种求和操作的控制单元。 计算机处理器还包括用于提供处理器输出作为反馈的开关。 由一组指令选择的指令由控制单元解码以配置计算机处理器对数据流执行操作。
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3.发明授权Computer processor having a pipelined architecture which utilizes feedback and method of using same 失效具有流水线结构的计算机处理器，其利用反馈和使用其的方法
公开(公告)号：US5761104A
公开(公告)日：1998-06-02
申请号：US751042
申请日：1996-11-15
CPC分类号： G06F7/4833 , G06F7/49 , G06F2207/3884
摘要： A computer processor that performs operations in a logarithmic number system (LNS) domain includes an input log converter (20), a feedback log converter (303), a first data pipeline (304), a second data pipeline (306), a plurality of processing elements (26a-f) coupled to respective stages of the data pipelines, an inverse-log converter (28), and a programmable accumulator (232) which produces output signals. An instruction, selected from a set of instructions, is decoded by a control unit (235) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters. The computer processor can be used as a co-processor (340) in a general purpose computer system.
摘要翻译： 执行对数编号系统（LNS）域中的操作的计算机处理器包括输入日志转换器（20），反馈日志转换器（303），第一数据流水线（304），第二数据流水线（306），多个 耦合到数据管线的各个级的处理元件（26a-f），反向对数转换器（28）和产生输出信号的可编程累加器（232）。 从一组指令中选择的指令由控制单元（235）解码，以配置计算机处理器对一个或多个数据流执行操作。 可以由处理器执行的数学运算包括矩阵乘法，矩阵反转，快速傅里叶变换（FFT），自相关，互相关，离散余弦变换（DCT），多项式方程和一般的差分方程，如 用于近似无限脉冲响应（IIR）和有限脉冲响应（FIR）滤波器的那些。 计算机处理器可以用作通用计算机系统中的协处理器（340）。
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公开(公告)号：US5726924A
公开(公告)日：1998-03-10
申请号：US680282
申请日：1996-07-11
申请人： John Michael Buss , James Douglas Dworkin , Scott Edward Lloyd , ShaoWei Pan , Stephen L. Smith , Shay-Ping Thomas Wang
发明人： John Michael Buss , James Douglas Dworkin , Scott Edward Lloyd , ShaoWei Pan , Stephen L. Smith , Shay-Ping Thomas Wang
CPC分类号： G06F7/556
摘要： A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.
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公开(公告)号：US5757960A
公开(公告)日：1998-05-26
申请号：US808707
申请日：1997-02-28
CPC分类号： G06K9/68 , G06K9/00409 , G06K9/00422
摘要： A handwriting recognition system achieves a higher recognition rate by using a feature extraction method which computes features based on multiple data frames. A plurality of data frames is generated from handwritten text received by the system. Each data frame includes samples taken from the handwritten text. Individual-frame features are extracted from individual data frames, and in turn, multi-frame features are extracted from individual-frame features which correspond to different data frames.
摘要翻译： 手写识别系统通过使用基于多个数据帧来计算特征的特征提取方法来实现更高的识别率。 从系统接收的手写文本生成多个数据帧。 每个数据帧包括从手写文本中取出的样本。 从单个数据帧提取单个帧特征，并且依次对应于不同数据帧的单帧特征提取多帧特征。
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公开(公告)号：US5642305A
公开(公告)日：1997-06-24
申请号：US381368
申请日：1995-01-31
申请人： ShaoWei Pan , Shay-Ping Thomas Wang
发明人： ShaoWei Pan , Shay-Ping Thomas Wang
CPC分类号： H03M7/50 , G06F1/0356 , G06F2101/10
摘要： A converter, which may be used for implementing either logarithmic or inverse-logarithmic functions, includes a memory, a multiplier, and an adder. The memory stores a plurality of parameters which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values.
摘要翻译： 可以用于实现对数或反对数函数的A转换器包括存储器，乘法器和加法器。 存储器存储使用最小二乘法导出的多个参数，以估计输入值的域上的对数或反对数函数。
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7.发明授权Logarithm/inverse-logarithm converter utilizing second-order term and method of using same 失效利用二阶项的对数/逆对数转换器及其使用方法
公开(公告)号：US5703801A
公开(公告)日：1997-12-30
申请号：US382467
申请日：1995-01-31
申请人： ShaoWei Pan , Shay-Ping Thomas Wang
发明人： ShaoWei Pan , Shay-Ping Thomas Wang
CPC分类号： G06F1/0356 , H03M7/50 , G06F2101/10
摘要： A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, a multiplier, and two adders. The memory stores a plurality of parameters and second-order terms which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of computing the parameters and second-order terms is also disclosed.
摘要翻译： 公开了可用于实现对数或反对数函数的转换器。 该转换器包括一个存储器，一个乘法器和两个加法器。 存储器存储使用最小二乘法导出的多个参数和二阶项，以估计输入值的域上的对数或反对数函数。 还公开了一种计算参数和二阶项的方法。
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8.发明授权
公开(公告)号：US5771391A
公开(公告)日：1998-06-23
申请号：US520666
申请日：1995-08-28
CPC分类号： G06F7/4833 , G06F17/10 , G06F1/0307 , G06F2207/3884 , G06F7/5235
摘要： A computer processor that performs operations in a logarithmic number system (LNS) domain includes a log converter (20) which generates log signals, a data pipeline (22), a plurality of processing elements (231a-f) coupled to respective stages (24a-d) of the data pipeline, an inverse-log converter (28), and a programmable accumulator (232) that performs various summing operations to produce an output signal. An instruction, selected from a set of instructions, is decoded by a control unit (234) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters. The computer processor can be used as a co-processor (340) in a general purpose computer system.
摘要翻译： 在对数数字系统（LNS）域中执行操作的计算机处理器包括生成日志信号的对数转换器（20），数据流水线（22），耦合到各个级（24a）的多个处理元件（231a-f） -d），反向对数转换器（28）和可编程累加器（232），其执行各种求和操作以产生输出信号。 从一组指令中选择的指令由控制单元（234）解码，以配置计算机处理器对一个或多个数据流执行操作。 可以由处理器执行的数学运算包括矩阵乘法，矩阵反转，快速傅里叶变换（FFT），自相关，互相关，离散余弦变换（DCT），多项式方程和一般的差分方程，如 用于近似无限脉冲响应（IIR）和有限脉冲响应（FIR）滤波器的那些。 计算机处理器可以用作通用计算机系统中的协处理器（340）。
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公开(公告)号：US5664192A
公开(公告)日：1997-09-02
申请号：US355738
申请日：1994-12-14
CPC分类号： G06F7/544
摘要： A method and system is described which allows execution overlap in a computer having a plurality of processing elements. The method and system provide an accumulation schedule based on the expected completion times of the processing elements. Outputs from the processing elements are accumulated according to the accumulation schedule. The accumulation schedule includes a plurality of accumulation flags which indicate when the outputs are to be accumulated.
摘要翻译： 描述了允许在具有多个处理元件的计算机中执行重叠的方法和系统。 方法和系统基于处理元件的预期完成时间提供累积调度。 来自处理元件的输出根据累计进度累积。 累积调度包括多个累积标志，其指示输出何时被累加。
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10.发明授权Computer processor having a pipelined architecture which utilizes feedback and method of using same 失效具有流水线结构的计算机处理器，其利用反馈和使用其的方法
公开(公告)号：US5657263A
公开(公告)日：1997-08-12
申请号：US520145
申请日：1995-08-28
CPC分类号： G06F7/4833 , G06F7/49 , G06F2207/3884
摘要： A computer processor that performs operations in a logarithmic number system (LNS) domain includes an input log converter (20), a feedback log converter (303), a first data pipeline (304), a second data pipeline (306), a plurality of processing elements (26a-f) coupled to respective stages of the data pipelines, an inverse-log converter (28), and a programmable accumulator (232) which produces output signals. An instruction, selected from a set of instructions, is decoded by a control unit (235) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters. The computer processor can be used as a co-processor (340) in a general purpose computer system.
摘要翻译： 执行对数编号系统（LNS）域中的操作的计算机处理器包括输入日志转换器（20），反馈日志转换器（303），第一数据流水线（304），第二数据流水线（306），多个 耦合到数据管线的各个级的处理元件（26a-f），反向对数转换器（28）和产生输出信号的可编程累加器（232）。 从一组指令中选择的指令由控制单元（235）解码，以配置计算机处理器对一个或多个数据流执行操作。 可以由处理器执行的数学运算包括矩阵乘法，矩阵反转，快速傅里叶变换（FFT），自相关，互相关，离散余弦变换（DCT），多项式方程和一般的差分方程，如 用于近似无限脉冲响应（IIR）和有限脉冲响应（FIR）滤波器的那些。 计算机处理器可以用作通用计算机系统中的协处理器（340）。
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