-
公开(公告)号：US20230335061A1
公开(公告)日：2023-10-19
申请号：US18028710
申请日：2020-10-02
Applicant: Sharp Kabushiki Kaisha
Inventor： Nobuyuki TAYA , Makoto YOKOYAMA , Naoki UEDA
IPC: G09G3/3266 , G11C19/28 , G09G3/3233
CPC classification number: G09G3/3266 , G09G3/3233 , G11C19/287 , G09G2300/0819 , G09G2300/0852 , G09G2310/0286 , G09G2310/08 , G09G2320/041 , G09G2320/043
Abstract: The scanning line drive circuit has a configuration in which a plurality of unit circuits are connected in multiple stages. A unit circuit includes: a first transistor having a first conductive terminal to which a first-level voltage is applied and a second conductive terminal connected to a first node; a second transistor having a second conductive terminal to which a second-level voltage is applied; a third transistor having a first conductive terminal connected to the first node and a second conductive terminal connected to a first conductive terminal of the second transistor; a fourth transistor having a first conductive terminal connected to a control terminal of the third transistor, and having a second conductive terminal and a control terminal to both of which the second-level voltage is applied; and an output transistor having a control terminal connected to the first node and a second conductive terminal connected to an output terminal.
-
公开(公告)号：US20230222981A1
公开(公告)日：2023-07-13
申请号：US18014493
申请日：2020-07-17
Applicant: Sharp Kabushiki Kaisha
Inventor： Makoto YOKOYAMA , Nobuyuki TAYA
IPC: G09G3/3266
CPC classification number: G09G3/3266 , G09G2310/0283 , G09G2310/0286 , G09G2300/0852
Abstract: Narrowing of a picture-frame of a display device that can perform switching between vertical scanning directions is implemented. A gate driver (21) includes a shift register (211) including a plurality of unit circuits including n unit circuits connected to write control lines; a first scanning order switching circuit (212) including a plurality of first switching circuits respectively corresponding to the plurality of unit circuits; and a second scanning order switching circuit (213) including n second switching circuits connected to initialization control lines. The first scanning order switching circuit (212) controls operation of the shift register (211) based on scanning order instruction signals. Each second switching circuit applies, based on the scanning order instruction signals, an output signal from a unit circuit on a previous stage side or an output signal from a unit circuit on a subsequent stage side, as a second scanning signal, to an initialization control line.
-
公开(公告)号：US20230112313A1
公开(公告)日：2023-04-13
申请号：US17908003
申请日：2020-03-02
Applicant: Sharp Kabushiki Kaisha
Inventor： Masahiro MITANI , Makoto YOKOYAMA , Naoki UEDA
IPC: G09G3/3266 , G09G3/3291 , G09G3/325
Abstract: Provided is a scanning-line driving circuit configured with a plurality of unit circuits cascaded in stages and integrally formed with a display panel. The unit circuit includes a first transistor, a resistor, a second transistor, and an output transistor. The first transistor has a first conductive electrode supplied with a first-level voltage and a second conductive electrode connected to a first node. The resistor is connected to the first node at a first terminal. The second transistor has a first conductive electrode supplied with a second-level voltage and a second conductive electrode connected to a second terminal of the resistor. The output transistor has a control electrode connected to the first node and a first conductive electrode connected to an output terminal. The resistor is formed in a semiconductor layer. The unit circuit further includes an upper electrode formed above the resistor. This configuration allows the scanning-line driving circuit to prevent an operation failure due to a change in characteristics of the resistor in the unit circuit.
-
公开(公告)号：US20210134930A1
公开(公告)日：2021-05-06
申请号：US17041918
申请日：2018-03-30
Applicant: SHARP KABUSHIKI KAISHA
Inventor： Makoto YOKOYAMA , Junichi YAMADA
Abstract: A frame region includes a first routed wire extending from one of a plurality of scan signal lines, one of a plurality of light-emission control lines, or one of a plurality of data signal lines. The first routed wire is electrically connected to drive circuits. The first routed wire is included in a first metal layer. A first conductive film is included in a second metal layer. The first routed wire and the first conductive film overlap each other via an inorganic insulating film.
-
Patent Agency Ranking
公开(公告)号：US20160027527A1
公开(公告)日：2016-01-28
申请号：US14775890
申请日：2014-02-17
Applicant: SHARP KABUSHIKI KAISHA
Inventor： Yuhichiroh MURAKAMI , Yasushi SASAKI , Shige FURUTA , Shuji NISHI , Makoto YOKOYAMA
CPC classification number: G11C19/28 , G09G3/3648 , G09G3/3677 , G09G2310/0286 , G09G2310/06
Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Tr2 switches between whether or not to provide an output of an on-potential output unit 2 to a gate terminal of Tr1 in accordance with an output of a set control unit 3. The set control unit 3 controls a gate terminal of Tr2 into a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr1. The gate potential of Tr2 is raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr1, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.
Abstract translation: 移位寄存器通过以多级连接单元电路1来配置。 输出晶体管Tr1根据栅极电位在是否输出时钟信号CKA之间切换。 设定晶体管Tr2根据设定控制单元3的输出，在是否向Tr1的栅极端子提供导通电位输出单元2的输出是否切换。设定控制单元3控制Tr2的栅极端子 在其中向Tr1的栅极端子提供高电平电压的时间段的一部分时间内成为浮置状态。 通过向上推动Tr2的栅极电位，由此向Tr1的栅极端子提供没有阈值下降的高电平电位，并且当输出信号OUT变为高电平时，输出信号OUT的舍入减小 。 因此，相对于晶体管的阈值电压的波动的操作余量增加。
-
公开(公告)号：US20160018844A1
公开(公告)日：2016-01-21
申请号：US14775884
申请日：2014-02-17
Applicant: SHARP KABUSHIKI KAISHA
Inventor： Yasushi SASAKI , Yuhichiroh MURAKAMI , Shuji NISHI , Takahiro YAMAGUCHI , Makoto YOKOYAMA
CPC classification number: G06F1/10 , G06F1/26 , G09G3/3677 , G09G2310/0286 , G11C19/28
Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A drain terminal of an initialization transistor Tra is connected to a gate terminal of the Tr1, and a source terminal thereof is connected to an output terminal OUT or a clock terminal CKA. The source terminal of the Tra is connected to a node which has a low-level potential at the time of initialization and has a potential at the same level as the clock signal when the clock signal having a high-level potential is outputted. Thus, at the time of outputting the clock signal having the high-level potential, application of a high voltage between the source and the drain of the Tra is prevented, and degradation and breakdown of the initialization transistor are prevented.
Abstract translation: 移位寄存器通过以多级连接单元电路1来配置。 输出晶体管Tr1根据栅极电位在是否输出时钟信号CKA之间切换。 初始化晶体管Tra的漏极端子连接到Tr1的栅极端子，其源极端子连接到输出端子OUT或时钟端子CKA。 Tra的源极端子连接到在初始化时具有低电位电位的节点，并且当输出具有高电位电位的时钟信号时，具有与时钟信号相同电平的电位。 因此，在输出具有高电位电位的时钟信号时，防止在Tra的源极和漏极之间施加高电压，并且防止初始化晶体管的劣化和击穿。
-
公开(公告)号：US20230024395A1
公开(公告)日：2023-01-26
申请号：US17783046
申请日：2019-12-13
Applicant: Sharp Kabushiki Kaisha
Inventor： Makoto YOKOYAMA , Nobuyuki TAYA , Junichi YAMADA
IPC: G09G3/3266
Abstract: In a display device having a non-rectangular display unit, occurrence of a difference in luminance between a region with a high load and a region with a low load is suppressed. A region inside the display unit is segmented into a high-load region with a high load on horizontal scanning lines (an initialization control line and a write control line) and a low-load region with a low load on horizontal scanning lines. An initialization control line and a write control line that are disposed in the high-load region are driven by a discharge driver and a scan driver, respectively. An initialization control line and a write control line that are disposed in the low-load region both are driven by, for example, the discharge driver.
-
公开(公告)号：US20200098316A1
公开(公告)日：2020-03-26
申请号：US16494810
申请日：2017-03-22
Applicant: Sharp Kabushiki Kaisha
Inventor： Makoto YOKOYAMA , Fumiyuki KOBAYASHI , Junichi YAMADA
IPC: G09G3/3258 , G09G3/20 , G09G3/3275 , G09G3/3266
Abstract: Provided are a display device drive method and a display device, both of which allow a pixel circuit to be discharged without leaving any electric charge in an OFF sequence for powering off the display device.During an OFF sequence period, a first node N1 is set to a first ground potential Vgnd1, which is a potential higher than an initialization potential Vini. As a result, even when a second ground potential Vgnd2 is supplied through a data line Dj to a second conductive terminal of a drive transistor T1, a gate terminal of the drive transistor T1 is not charged with a gate-to-source voltage Vgs. Therefore, an organic EL display device 1 is powered off with the gate terminal of the drive transistor T1 being charged with the first ground potential Vgnd1 leaving no electric charge in a pixel circuit 11 after the power off.
-
公开(公告)号：US20170162158A1
公开(公告)日：2017-06-08
申请号：US15323990
申请日：2015-07-03
Applicant: Sharp Kabushiki Kaisha
Inventor： Tatsuhiko SUYAMA , Norio OHMURA , Noriyuki TANAKA , Makoto YOKOYAMA
CPC classification number: G09G3/3677 , G06F1/3265 , G09G3/3611 , G09G3/3648 , G09G3/3688 , G09G2310/04 , G09G2310/08 , G09G2330/00 , G09G2330/021 , G09G2360/12 , G09G2360/18
Abstract: In a liquid crystal display device, it is determined whether or not image data inputted from the outside has changed from image data of the previous frame by comparing those image data with respect to each line. As a result, when it is determined that the image data has changed, an entire screen is not rewritten, but image data from a top of a screen as a fixed position to a last line with the image data having changed are read from a frame memory and written into a pixel formation portion. Accordingly, of the screen for one frame, a screen from a top thereof to the last line where the image change has been detected is updated, and on subsequent lines, an image of the previous frame is continuously displayed.
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.02 seconds)
