公开(公告)号：US5753548A

公开(公告)日：1998-05-19

申请号：US719234

申请日：1996-09-24

申请人： Shau-Tsung Yu ,  An-Min Chiang ,  Yeh-Jye Wann ,  Pei-Hung Chen

发明人： Shau-Tsung Yu ,  An-Min Chiang ,  Yeh-Jye Wann ,  Pei-Hung Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814

摘要： A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs by alternate photoresist masking and ion implantation. The shallow junction self-aligned source/drain areas for P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions implanted in the P-channel FET gate electrodes during the source/drain implant results in outgassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which uses a photoresist block-out mask to eliminate the implantation of the BF.sub.2.sup.+ ions in the P-channel FET gate electrodes during the formation of the self-aligned P.sup.+ source/drain regions. This prevents voids from forming at the gate electrode/ILD interface after the ILD layer is deposited and subsequent high-temperature processing steps are performed. The invention also reduces the enhanced boron diffusion in the P-FET gate oxide that can degrade the threshold voltage.

摘要翻译： 描述了一种用于形成具有浅源极/漏极结的P沟道场效应晶体管和用于CMOS电路的改善的可靠性的方法。 该方法包括通过交替的光刻胶掩模和离子注入形成N沟道和P沟道FET。 用于P沟道FET的浅结自对准源极/漏极区域是通过注入二氟化硼（BF 2）离子形成的。 在更常规的处理中，在源极/漏极注入期间注入到P沟道FET栅电极中的BF 2离子导致沉积了层间电介质（ILD）层之后，从栅电极释放氟。 这可能导致在栅电极和ILD之间的界面处的空隙形成或分层。 本发明提供了一种改进的方法，其使用光致抗蚀剂阻挡掩模以在形成自对准P +源极/漏极区域期间消除P沟道FET栅极中的BF 2 +离子的注入。 这防止了在淀积ILD层之后在栅电极/ ILD界面处形成空隙，并且执行随后的高温处理步骤。 本发明还减少了可能降低阈值电压的P-FET栅极氧化物中增强的硼扩散。

公开(公告)号：US5707896A

公开(公告)日：1998-01-13

申请号：US714734

申请日：1996-09-16

申请人： An-Min Chiang ,  Shau-Tsung Yu ,  Yeh-Jye Wann ,  Pei-Hung Chen

发明人： An-Min Chiang ,  Shau-Tsung Yu ,  Yeh-Jye Wann ,  Pei-Hung Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814

摘要： A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs on the same substrate by alternate photoresist masking and ion implantation. The self-aligned source/drain areas for the P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions that are implanted in the P-channel FET gate electrodes during the source/drain implant results in out-gassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which out-diffuses the fluorine atoms prior to depositing the ILD, and thereby prevents the formation of voids after the ILD is deposited and subsequent high-temperature process steps are performed.

摘要翻译： 描述了一种用于形成具有浅源极/漏极结的P沟道场效应晶体管和用于CMOS电路的改善的可靠性的方法。 该方法包括通过交替的光刻胶掩模和离子注入在同一衬底上形成N沟道和P沟道FET。 用于P沟道FET的自对准源极/漏极区域通过注入二氟化硼（BF 2）离子形成。 在更常规的处理中，在源极/漏极注入期间注入到P沟道FET栅电极中的BF 2离子导致在沉积层间电介质（ILD）层之后，从栅电极排出氟。 这可能导致在栅电极和ILD之间的界面处的空隙形成或分层。 本发明提供了一种改进的方法，其在沉积ILD之前扩散氟原子，从而防止在沉积ILD之后形成空隙并进行随后的高温处理步骤。

公开(公告)号：US5652172A

公开(公告)日：1997-07-29

申请号：US639679

申请日：1996-04-29

申请人： Peng Yung-Sung ,  An Min Chiang ,  Shau-Tsung Yu ,  Min-Yi Lin

发明人： Peng Yung-Sung ,  An Min Chiang ,  Shau-Tsung Yu ,  Min-Yi Lin

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/31105 ,  H01L21/31144 ,  H01L21/76804

摘要： A method for forming an aperture with a uniform void-free sidewall etch profile through a multi-layer insulator layer. There is formed upon a semiconductor substrate a multi-layer insulator layer which has a minimum of a first insulator layer and a second insulator layer. The second insulator layer is formed upon the first insulator layer. There is then etched through a first etch method a first aperture completely through the second insulator layer. The first etch method has: (1) a first perpendicular etch selectivity ratio for the second insulator layer with respect to the first insulator layer of at least about 4:1; and (2) a lateral:perpendicular etch selectivity ratio for the second insulator layer of from about 0.5:1 to about 1:1. The first aperture is then etched through a second etch method to form a second aperture completely through the second insulator layer and the first insulator layer. The second etch method has: (1) a second perpendicular etch selectivity ratio for the second insulator layer with respect to the first insulator layer of no greater than about 2:1; and (2) a lateral etch selectivity ratio of the second insulator layer with respect to the first insulator layer of from about 0.5:1 to about 1:1. The second aperture has a uniform void-free sidewall etch profile.

摘要翻译： 一种通过多层绝缘体层形成具有均匀无空隙侧壁蚀刻轮廓的孔的方法。 在半导体衬底上形成具有最小第一绝缘体层和第二绝缘体层的多层绝缘体层。 第二绝缘体层形成在第一绝缘体层上。 然后通过第一蚀刻方法蚀刻完全穿过第二绝缘体层的第一孔。 第一蚀刻方法具有：（1）第二绝缘体层相对于第一绝缘体层的第一垂直蚀刻选择比为至少约4:1; 和（2）第二绝缘体层的横向：垂直蚀刻选择比为约0.5:1至约1:1。 然后通过第二蚀刻方法蚀刻第一孔，以完全穿过第二绝缘体层和第一绝缘体层形成第二孔。 第二蚀刻方法具有：（1）第二绝缘体层相对于第一绝缘体层的第二垂直蚀刻选择比不大于约2:1; 和（2）第二绝缘体层相对于第一绝缘体层的横向蚀刻选择比为约0.5:1至约1:1。 第二孔具有均匀的无空隙侧壁蚀刻轮廓。

公开(公告)号：US6020241A

公开(公告)日：2000-02-01

申请号：US995338

申请日：1997-12-22

申请人： Jyh-Cheng You ,  Pei-Hung Chen ,  Shau-Tsung Yu ,  Yi-Jing Chu

发明人： Jyh-Cheng You ,  Pei-Hung Chen ,  Shau-Tsung Yu ,  Yi-Jing Chu

IPC分类号： H01L21/8246 ,  H01L21/8236

CPC分类号： H01L27/11293 ,  H01L27/1126

摘要： The present invention provides a method of manufacturing a read only memory that is code implanted late in the process after the first level metal thus reducing the turn around time to ship a customer order. The invention comprising the steps of: forming bit lines 125 and word lines 160 in a cell area 12A and MOS transistors in a peripheral area 13 of an integrated circuit; forming a first dielectric layer 300 over the surface; etching back the first dielectric layer 300 in the cell area; forming metal contacts 700 to the MOS devices in the peripheral areas 13; forming the second dielectric layer 320 over the resultant surface, storing the integrated circuit; and programming the ROM region 12A by the steps of forming a Code mask 340 with openings 340A from over portions of word lines in the cell area and implanting impurities through the openings 340A into substrate under the selected word lines 160 thereby programming the ROM device.

摘要翻译： 本发明提供了一种制造只读存储器的方法，该只读存储器是在第一级金属之后的过程中植入的代码，因此减少了轮询周转时间来运送客户订单。 本发明包括以下步骤：在单元区域12A中形成位线125和字线160，并在集成电路的外围区域13中形成MOS晶体管; 在表面上形成第一电介质层300; 在单元区域中蚀刻第一介电层300; 将金属触点700形成到周边区域13中的MOS器件; 在所得表面上形成第二电介质层320，存储集成电路; 并且通过以下步骤对ROM区域12A进行编程：步骤：从单元区域中的字线的多个部分形成具有开口340A的代码掩码340，并且通过开口340A将杂质注入到所选字线160之下的衬底中，从而对ROM器件进行编程。