公开(公告)号：US5753548A

公开(公告)日：1998-05-19

申请号：US719234

申请日：1996-09-24

申请人： Shau-Tsung Yu ,  An-Min Chiang ,  Yeh-Jye Wann ,  Pei-Hung Chen

发明人： Shau-Tsung Yu ,  An-Min Chiang ,  Yeh-Jye Wann ,  Pei-Hung Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814

摘要： A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs by alternate photoresist masking and ion implantation. The shallow junction self-aligned source/drain areas for P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions implanted in the P-channel FET gate electrodes during the source/drain implant results in outgassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which uses a photoresist block-out mask to eliminate the implantation of the BF.sub.2.sup.+ ions in the P-channel FET gate electrodes during the formation of the self-aligned P.sup.+ source/drain regions. This prevents voids from forming at the gate electrode/ILD interface after the ILD layer is deposited and subsequent high-temperature processing steps are performed. The invention also reduces the enhanced boron diffusion in the P-FET gate oxide that can degrade the threshold voltage.

摘要翻译： 描述了一种用于形成具有浅源极/漏极结的P沟道场效应晶体管和用于CMOS电路的改善的可靠性的方法。 该方法包括通过交替的光刻胶掩模和离子注入形成N沟道和P沟道FET。 用于P沟道FET的浅结自对准源极/漏极区域是通过注入二氟化硼（BF 2）离子形成的。 在更常规的处理中，在源极/漏极注入期间注入到P沟道FET栅电极中的BF 2离子导致沉积了层间电介质（ILD）层之后，从栅电极释放氟。 这可能导致在栅电极和ILD之间的界面处的空隙形成或分层。 本发明提供了一种改进的方法，其使用光致抗蚀剂阻挡掩模以在形成自对准P +源极/漏极区域期间消除P沟道FET栅极中的BF 2 +离子的注入。 这防止了在淀积ILD层之后在栅电极/ ILD界面处形成空隙，并且执行随后的高温处理步骤。 本发明还减少了可能降低阈值电压的P-FET栅极氧化物中增强的硼扩散。

公开(公告)号：US5707896A

公开(公告)日：1998-01-13

申请号：US714734

申请日：1996-09-16

申请人： An-Min Chiang ,  Shau-Tsung Yu ,  Yeh-Jye Wann ,  Pei-Hung Chen

发明人： An-Min Chiang ,  Shau-Tsung Yu ,  Yeh-Jye Wann ,  Pei-Hung Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814

摘要： A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs on the same substrate by alternate photoresist masking and ion implantation. The self-aligned source/drain areas for the P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions that are implanted in the P-channel FET gate electrodes during the source/drain implant results in out-gassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which out-diffuses the fluorine atoms prior to depositing the ILD, and thereby prevents the formation of voids after the ILD is deposited and subsequent high-temperature process steps are performed.

摘要翻译： 描述了一种用于形成具有浅源极/漏极结的P沟道场效应晶体管和用于CMOS电路的改善的可靠性的方法。 该方法包括通过交替的光刻胶掩模和离子注入在同一衬底上形成N沟道和P沟道FET。 用于P沟道FET的自对准源极/漏极区域通过注入二氟化硼（BF 2）离子形成。 在更常规的处理中，在源极/漏极注入期间注入到P沟道FET栅电极中的BF 2离子导致在沉积层间电介质（ILD）层之后，从栅电极排出氟。 这可能导致在栅电极和ILD之间的界面处的空隙形成或分层。 本发明提供了一种改进的方法，其在沉积ILD之前扩散氟原子，从而防止在沉积ILD之后形成空隙并进行随后的高温处理步骤。

公开(公告)号：US5811343A

公开(公告)日：1998-09-22

申请号：US683645

申请日：1996-07-15

申请人： Yeh-Jye Wann ,  An-Min Chiang ,  Shaun-Tsung Yu ,  Pei-Hung Chen

发明人： Yeh-Jye Wann ,  An-Min Chiang ,  Shaun-Tsung Yu ,  Pei-Hung Chen

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/265

CPC分类号： H01L29/66575 ,  H01L21/8234

摘要： A method for manufacturing integrated circuit semiconductor device is provided for doping polysilicon formed on an N-well in a semiconductor substrate. Form a silicon oxide layer on the N-well. Then form a blanket polysilicon layer over the silicon oxide layer and pattern the polysilicon layer into a structure. Form a sacrificial oxide layer over the polysilicon structure. Then ion implant .sup.49 (BF.sub.2).sup.+ ions into the N-well and the polysilicon layer forming the source/drain regions and doping the polysilicon layer with P-type dopant thereby forming a doped polysilicon layer from the polysilicon layer. Then etch the sacrificial oxide layer away from the device. Form a polyoxide layer over the polysilicon structure. Then form a silicon oxide layer over the polyoxide layer followed by forming a glass layer thereover.

摘要翻译： 提供一种用于制造集成电路半导体器件的方法，用于掺杂形成在半导体衬底中的N阱上的多晶硅。 在N阱上形成氧化硅层。 然后在氧化硅层上形成覆盖多晶硅层，并将多晶硅层图案化成结构。 在多晶硅结构上形成牺牲氧化层。 然后将离子注入49（BF 2）+离子注入N阱和形成源极/漏极区的多晶硅层，并用P型掺杂剂掺杂多晶硅层，从而从多晶硅层形成掺杂多晶硅层。 然后将牺牲氧化层蚀刻离开器件。 在多晶硅结构上形成多氧化物层。 然后在多氧化物层上形成氧化硅层，然后在其上形成玻璃层。

公开(公告)号：US6020241A

公开(公告)日：2000-02-01

申请号：US995338

申请日：1997-12-22

申请人： Jyh-Cheng You ,  Pei-Hung Chen ,  Shau-Tsung Yu ,  Yi-Jing Chu

发明人： Jyh-Cheng You ,  Pei-Hung Chen ,  Shau-Tsung Yu ,  Yi-Jing Chu

IPC分类号： H01L21/8246 ,  H01L21/8236

CPC分类号： H01L27/11293 ,  H01L27/1126

摘要： The present invention provides a method of manufacturing a read only memory that is code implanted late in the process after the first level metal thus reducing the turn around time to ship a customer order. The invention comprising the steps of: forming bit lines 125 and word lines 160 in a cell area 12A and MOS transistors in a peripheral area 13 of an integrated circuit; forming a first dielectric layer 300 over the surface; etching back the first dielectric layer 300 in the cell area; forming metal contacts 700 to the MOS devices in the peripheral areas 13; forming the second dielectric layer 320 over the resultant surface, storing the integrated circuit; and programming the ROM region 12A by the steps of forming a Code mask 340 with openings 340A from over portions of word lines in the cell area and implanting impurities through the openings 340A into substrate under the selected word lines 160 thereby programming the ROM device.

摘要翻译： 本发明提供了一种制造只读存储器的方法，该只读存储器是在第一级金属之后的过程中植入的代码，因此减少了轮询周转时间来运送客户订单。 本发明包括以下步骤：在单元区域12A中形成位线125和字线160，并在集成电路的外围区域13中形成MOS晶体管; 在表面上形成第一电介质层300; 在单元区域中蚀刻第一介电层300; 将金属触点700形成到周边区域13中的MOS器件; 在所得表面上形成第二电介质层320，存储集成电路; 并且通过以下步骤对ROM区域12A进行编程：步骤：从单元区域中的字线的多个部分形成具有开口340A的代码掩码340，并且通过开口340A将杂质注入到所选字线160之下的衬底中，从而对ROM器件进行编程。

公开(公告)号：US6159660A

公开(公告)日：2000-12-12

申请号：US794694

申请日：1997-02-03

申请人： Hsin-Pai Chen ,  An-Min Chiang ,  Pei-Hung Chen

发明人： Hsin-Pai Chen ,  An-Min Chiang ,  Pei-Hung Chen

IPC分类号： G03F7/20 ,  H01L21/027 ,  H01L21/3213 ,  G03F7/207

CPC分类号： G03F7/70425 ,  G03F7/20 ,  H01L21/0274 ,  H01L21/32139

摘要： A method of forming a number of closely spaced electrodes is described wherein covering the electrodes with a conformal layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition does not result in the formation of restricted regions or keyholes between adjacent electrodes. The method uses de-focussing to form the electrode mask pattern in a layer of photoresist. The focal plane in which the electrode pattern is focussed is positioned a de-focus distance above the layer of photoresist. The de-focus method results in electrodes having a trapezoidal cross section wherein the bottom of the electrode is wider than the top of the electrode. The trapezoidal cross section avoids the formation of restricted regions or keyholes when the electrodes are covered with a conformal dielectric layer, such as a layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition.

摘要翻译： 描述了形成多个紧密间隔的电极的方法，其中使用等离子体增强化学气相沉积沉积的氧化物或氮化物的保形层覆盖电极不会导致在相邻电极之间形成受限制的区域或键孔。 该方法使用去焦点在光致抗蚀剂层中形成电极掩模图案。 电极图案聚焦的焦平面位于光致抗蚀剂层之上的去焦距离。 脱焦方法导致具有梯形横截面的电极，其中电极的底部比电极的顶部宽。 梯形横截面避免了当电极覆盖有保形介质层（例如使用等离子体增强化学气相沉积沉积的氧化物或氮化物层）时形成限制区域或键孔。

公开(公告)号：US20130288436A1

公开(公告)日：2013-10-31

申请号：US13459379

申请日：2012-04-30

申请人： Chun-Li Chou ,  Shao-Yen Ku ,  Pei-Hung Chen ,  Jui-Ping Chuang

发明人： Chun-Li Chou ,  Shao-Yen Ku ,  Pei-Hung Chen ,  Jui-Ping Chuang

IPC分类号： H01L21/336 ,  C11D3/28

CPC分类号： H01L27/088 ,  C11D7/3209 ,  C11D7/3281 ,  C11D7/34 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7848

摘要： Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used.

摘要翻译： 一些实施例涉及半导体器件的制造方法。 在该方法中，提供了包括其上的金属栅电极的半导体工件。 在半导体工件中形成开口以暴露金属栅极的表面。 开口的形成在工件上留下聚合物残留物。 为了从工件中除去聚合物残渣，使用包含有机碱组分的清洁溶液。

公开(公告)号：US06642150B1

公开(公告)日：2003-11-04

申请号：US09473029

申请日：1999-12-28

申请人： Chuan-Chieh Huang ,  Wen-Hsiang Tang ,  Ming-Shuo Yen ,  Chiang-Jen Peng ,  Pei-Hung Chen

发明人： Chuan-Chieh Huang ,  Wen-Hsiang Tang ,  Ming-Shuo Yen ,  Chiang-Jen Peng ,  Pei-Hung Chen

IPC分类号： H01L21302

CPC分类号： H01L22/24 ,  G01N21/95692 ,  H01L22/34

摘要： A new method for detecting blind holes in the contact layer of a multi-chip semiconductor test wafer makes use of the fact that if the hole is not a blind hole, a subsequent etch step extends the hole a predetermined distance into the layer immediately underlying the contact layer. After a predetermined number of holes have been etched through the contact layer and for a predetermined distance into the layer underlying the contact layer, the contact layer is stripped to expose the holes in the underlying layer. These holes are scanned optically by a commercial apparatus that ordinarily detects wafer defects that resemble the holes. The missing holes are detected by comparing the holes of different chips on the test wafer. The test is particularly useful with a high density plasma etch because these holes typically have a very small diameter in relation to the thickness of the contact layer.

摘要翻译： 用于检测多芯片半导体测试晶片的接触层中的盲孔的新方法利用以下事实：如果孔不是盲孔，则随后的蚀刻步骤将孔延伸到紧邻下面的层中的预定距离 接触层。 在已经通过接触层蚀刻了预定数量的孔并且进入到接触层下面的预定距离之前，剥离接触层以露出下层中的孔。 这些孔由通常检测类似于孔的晶片缺陷的商业设备进行光学扫描。 通过比较测试晶片上不同芯片的孔来检测缺失的孔。 该测试对于高密度等离子体蚀刻特别有用，因为这些孔通常相对于接触层的厚度具有非常小的直径。

公开(公告)号：US5658821A

公开(公告)日：1997-08-19

申请号：US721668

申请日：1996-09-27

申请人： Hsin-Pai Chen ,  Sue-Mei Ku ,  Pei-Hung Chen ,  Chih-Shih Wei

发明人： Hsin-Pai Chen ,  Sue-Mei Ku ,  Pei-Hung Chen ,  Chih-Shih Wei

IPC分类号： H01L21/02 ,  H01L21/321 ,  H01L21/70

CPC分类号： H01L28/40 ,  H01L21/32105

摘要： A method of forming capacitors comprising polysilicon, polysilicon oxide, metal is described which significantly improves uniformity of capacitance across the silicon integrated circuit wafer and avoids damage to electrical contact regions. A first layer of polysilicon oxide is formed on a polysilicon first capacitor plate. The wafer is then dipped in a buffered oxide etch or subjected to a dry anisotropic etch. The etching conditions the polysilicon layer so that subsequent polysilicon oxide growth is very uniform and controllable. A second polysilicon oxide layer is then formed on the polysilicon first capacitor plate. A layer of silicon nitride is formed on the polysilicon oxide and a second capacitor plate is formed on the layer of silicon nitride completing the capacitor. Improved capacitance uniformity across the wafer is achieved and device damage is avoided.

摘要翻译： 描述了形成包括多晶硅，多晶硅氧化物，金属的电容器的方法，其显着地提高了跨越硅集成电路晶片的电容的均匀性并且避免了对电接触区域的损坏。 在多晶硅第一电容器板上形成第一层多晶硅氧化物。 然后将晶片浸入缓冲氧化物蚀刻中或进行干法各向异性蚀刻。 蚀刻条件使多晶硅层成为后续的多晶硅氧化物生长非常均匀和可控的。 然后在多晶硅第一电容器板上形成第二多晶硅氧化物层。 在多晶硅氧化物上形成氮化硅层，在形成电容器的氮化硅层上形成第二电容器板。 实现了跨晶片的改善的电容均匀性，避免了器件损坏。

公开(公告)号：US06267121B1

公开(公告)日：2001-07-31

申请号：US09248343

申请日：1999-02-11

申请人： Cheng-Hao Huang ,  Ming-Shuo Yen ,  Shih-Fang Chen ,  Wen-Hsiang Tang ,  Pei-Hung Chen

发明人： Cheng-Hao Huang ,  Ming-Shuo Yen ,  Shih-Fang Chen ,  Wen-Hsiang Tang ,  Pei-Hung Chen

IPC分类号： B08B500

CPC分类号： H01L21/67276 ,  H01L21/67069 ,  H01L21/67253 ,  Y10S438/905

摘要： An improved seasoning process for a plasma etching chamber is described. This has been achieved by increasing the RF power to both the wafer and the walls of the chamber during seasoning. Additionally, the gas that is used is at a pressure of about 10 mTorr and has the following composition: chlorine about 90% and oxygen about 10%. By observing the optical emission spectrum during seasoning (notably lines due to the SiClx species) it is confirmed that, under these conditions, seasoning is completed by using only a single wafer for about 100 seconds.

摘要翻译： 描述了用于等离子体蚀刻室的改进的调味过程。 这是通过在调味期间增加晶片和室壁的RF功率来实现的。 另外，使用的气体的压力为约10mTorr，具有以下组成：氯约90％，氧约10％。 通过观察调味期间的光发射光谱（特别是由于SiClx物质引起的线），证实在这些条件下，通过仅使用单个晶片约100秒完成调味。

公开(公告)号：US20050151969A1

公开(公告)日：2005-07-14

申请号：US10757204

申请日：2004-01-14

申请人： Chih-Ming Ke ,  Pei-Hung Chen ,  Shinn-Sheng Yu

发明人： Chih-Ming Ke ,  Pei-Hung Chen ,  Shinn-Sheng Yu

IPC分类号： G01J4/00 ,  G01N21/21 ,  G01N21/84

CPC分类号： G01N21/211 ,  G01N21/8422 ,  G01N2021/213

摘要： A method of determining optical constants n and k for a film on a substrate is described. Optical measurements are preferably performed with an integrated optical measurement system comprising a reflectometer, spectral ellipsometer, and broadband spectrometer such as an Opti-Probe series tool from Therma-Wave. A beam profile reflectometer is employed to first determine the thickness of said film from a best fit of modeling data to experimental data. The thickness data is combined with the ellipsometer and spectrometer measurements to produce an experimental data output which is fitted with modeled information to determine a best fit of the data. Constants n and k are derived from the best fit of data. The method provides a higher accuracy for n and k values than by standard procedures which calculate n, k, and t simultaneously. The method may also be applied to bilayer or multi-layer film stacks.

摘要翻译： 描述了确定基板上的膜的光学常数n和k的方法。 光学测量优选用包括反射计，光谱椭偏仪和宽带光谱仪的集成光学测量系统进行，例如来自Therma-Wave的Opti-Probe系列工具。 使用光束轮廓反射计首先从建模数据到实验数据的最佳拟合来确定所述膜的厚度。 将厚度数据与椭偏仪和光谱仪测量结合，以产生一个实验数据输出，该数据输出装配有建模信息以确定数据的最佳拟合。 常数n和k是从数据的最佳拟合得出的。 该方法对于n和k值提供比通过同时计算n，k和t的标准程序更高的精度。 该方法也可以应用于双层膜或多层膜堆叠。