公开(公告)号：US06925517B2

公开(公告)日：2005-08-02

申请号：US10249361

申请日：2003-04-03

申请人： Sheng-Chang Peng ,  Chau-Chad Tsai ,  Chih-kuo Kao ,  Chi-Che Tsai

发明人： Sheng-Chang Peng ,  Chau-Chad Tsai ,  Chih-kuo Kao ,  Chi-Che Tsai

IPC分类号： H04L5/16 ,  G06F13/14 ,  G06F13/40

CPC分类号： H04L5/16

摘要： A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer load in between the control chips is suitable for the bi-direction transfer, the signal line configuration of the bi-direction transfer is selected. When the direction of the bi-direction transfer switches frequently, the other signal line configuration is selected. That is, the bus signal lines are divided into two parts, each part is in charge of the data transfer in each uni-direction to avoid the turn around cycle that impacts the transfer performance.

摘要翻译： 用于支持多个信号线配置的总线及其切换方法，用于在控制芯片之间的总线中操作以保持其操作灵活性。 当控制芯片之间的数据传输负载适用于双向传输时，选择双向传输的信号线配置。 当双向传输方向频繁切换时，选择其他信号线配置。 也就是说，总线信号线分为两部分，每个部分负责每个单向的数据传输，以避免影响传输性能的转向周期。

公开(公告)号：US08060676B2

公开(公告)日：2011-11-15

申请号：US11433195

申请日：2006-05-11

申请人： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

发明人： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

IPC分类号： G06F13/42 ,  G06F5/06 ,  G06F13/36

CPC分类号： G06F13/423 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

摘要翻译： 本发明提供了一种在总线上热切换数据传输速率的方法，以热切换控制芯片之间的总线的数据传输速率，而无需复位。 当控制芯片之间的总线需要大量的数据传输时，总线被热切换到更高的数据传输速率，以满足数据传输的要求。 相反，当控制芯片之间的总线需要更少的数据传输量时，总线被热切换到较低的数据传输速率以节省功耗。

公开(公告)号：US20060206644A1

公开(公告)日：2006-09-14

申请号：US11433195

申请日：2006-05-11

申请人： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

发明人： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

IPC分类号： G06F13/42

CPC分类号： G06F13/423 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

公开(公告)号：US06571323B2

公开(公告)日：2003-05-27

申请号：US10115780

申请日：2002-04-03

申请人： Jiin Lai ,  Chih-kuo Kao

发明人： Jiin Lai ,  Chih-kuo Kao

IPC分类号： G06F1200

CPC分类号： G06F12/0895 ,  G06F12/0215 ,  G06F12/123

摘要： A memory-access management method and system is provided for use with an DRAM (Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system has a managing device for managing the N memory pages. According to the embodiment, the managing device further comprises a page register unit. The page register unit is used for storing K storage units, each of which stores an address data of the memory page. The utilization-rate register unit is coupled to the page register circuit, and used for monitoring utilizations of the storage units. In practical design, the number K of the storage units can be designed to be less than the number N of the memory pages.

公开(公告)号：US06490665B1

公开(公告)日：2002-12-03

申请号：US09350974

申请日：1999-07-09

申请人： Jiin Lai ,  Chih-kuo Kao ,  Chia-Hsin Chen

发明人： Jiin Lai ,  Chih-kuo Kao ,  Chia-Hsin Chen

IPC分类号： G06F1200

CPC分类号： G06F12/0895 ,  G06F12/123

摘要： A memory-access management method and system is provided for use with an SDRAM (Synchronous Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system includes a page-table register unit including a page table for storing a predefined number of recently accessed memory locations of the memory unit. Further, the memory-page management system includes a comparison unit capable of, in response to each access request to the memory unit, checking whether the requested memory location is a hit to any one stored in the page table in the page-table register unit. A utilization-rate register unit is coupled to the page-table register unit for monitoring the least-recently-used records stored in the page-table register unit; and moreover, a validity-checking unit is coupled to the page-table register unit for checking whether the address data stored in the page table in the page-table register unit is valid or invalid.

摘要翻译： 提供了一种与SDRAM（同步动态随机存取存储器）等一起使用的存储器访问管理方法和系统，用于通过跟踪存储器访问历史来增加对SDRAM的存储器访问的性能 以前的访问操作。 存储器页管理系统包括页表寄存器单元，其包括用于存储存储器单元的预定数量的最近访问的存储器位置的页表。 此外，存储器页管理系统包括：比较单元，其能够响应于对存储器单元的每个访问请求，检查所请求的存储器位置是否是存储在页表寄存器单元中的页表中的任何一个的命中 。 利用率寄存器单元耦合到页表寄存器单元，用于监视存储在页表寄存器单元中的最近最少使用的记录; 此外，有效性检查单元耦合到页表寄存器单元，用于检查存储在页表寄存器单元中的页表中的地址数据是有效还是无效。