公开(公告)号：US08343840B2

公开(公告)日：2013-01-01

申请号：US12763006

申请日：2010-04-19

申请人： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

发明人： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L27/115 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792

摘要： A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

摘要翻译： 带隙设计的电荷捕获存储单元包括电荷捕获元件，其通过具有介电常数的金属掺杂氧化硅材料的阻挡层（例如掺铝氧化硅）与栅极分离，并与半导体本体分离，包括 通道由工程隧道电介质。

公开(公告)号：US20110003452A1

公开(公告)日：2011-01-06

申请号：US12881570

申请日：2010-09-14

申请人： SHENG CHIH LAI ,  Hang-Ting Lue ,  Chien Wei Liao

发明人： SHENG CHIH LAI ,  Hang-Ting Lue ,  Chien Wei Liao

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/28282 ,  G11C8/10 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

摘要翻译： 阻挡介电工程的电荷捕获存储单元包括电荷俘获元件，其通过阻挡电介质与栅极分离，所述阻挡电介质包括与电荷俘获元件接触的缓冲层，例如可以以高质量制造的二氧化硅，以及 与栅极和沟道中的所述一个接触的第二覆盖层。 覆盖层的介电常数高于第一层的介电常数，优选包括高<！ - SIPO

公开(公告)号：US20090039416A1

公开(公告)日：2009-02-12

申请号：US11845321

申请日：2007-08-27

申请人： Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

发明人： Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792

摘要： A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

摘要翻译： 带隙设计的电荷捕获存储单元包括电荷捕获元件，其通过具有介电常数的金属掺杂氧化硅材料的阻挡层（例如掺铝氧化硅）与栅极分离，并与半导体本体分离，包括 通道由工程隧道电介质。

公开(公告)号：US07737488B2

公开(公告)日：2010-06-15

申请号：US11845321

申请日：2007-08-27

申请人： Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

发明人： Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792

摘要： A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

摘要翻译： 带隙设计的电荷捕获存储单元包括电荷捕获元件，其通过具有介电常数的金属掺杂氧化硅材料的阻挡层（例如掺铝氧化硅）与栅极分离，并与半导体本体分离，包括 通道由工程隧道电介质。

公开(公告)号：US08119481B2

公开(公告)日：2012-02-21

申请号：US12881570

申请日：2010-09-14

申请人： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

发明人： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  G11C8/10 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

公开(公告)号：US20090059676A1

公开(公告)日：2009-03-05

申请号：US12182318

申请日：2008-07-30

申请人： Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

发明人： Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

IPC分类号： G11C11/34 ,  H01L29/792 ,  H01L21/28

CPC分类号： H01L21/28282 ,  G11C8/10 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric comprising a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably comprises a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

摘要翻译： 阻挡介电工程的电荷捕获存储单元包括电荷俘获元件，其通过阻挡电介质与栅极分离，该阻挡电介质包括与电荷俘获元件接触的缓冲层，例如可以制造高质量的二氧化硅，以及 与栅极和沟道中的所述一个接触的第二覆盖层。 封盖层的介电常数高于第一层，并且优选包含高卡宾材料。 第二层也具有相对高的导带偏移。 提供了通道和电荷捕获元件之间的带隙设计的隧穿层，其与本文所述的多层阻挡电介质组合，通过空穴隧穿提供高速擦除操作。 替代地，使用单层隧穿层。

公开(公告)号：US08330210B2

公开(公告)日：2012-12-11

申请号：US13398825

申请日：2012-02-16

申请人： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

发明人： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  G11C8/10 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

摘要翻译： 阻挡介电工程的电荷捕获存储单元包括电荷俘获元件，其通过阻挡电介质与栅极分离，所述阻挡电介质包括与电荷俘获元件接触的缓冲层，例如可以以高质量制造的二氧化硅，以及 与栅极和沟道中的所述一个接触的第二覆盖层。 覆盖层的介电常数高于第一层的介电常数，优选包括高<！ - SIPO

公开(公告)号：US20120146126A1

公开(公告)日：2012-06-14

申请号：US13398825

申请日：2012-02-16

申请人： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

发明人： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L21/28282 ,  G11C8/10 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

摘要翻译： 阻挡介电工程的电荷捕获存储单元包括电荷俘获元件，其通过阻挡电介质与栅极分离，所述阻挡电介质包括与电荷俘获元件接触的缓冲层，例如可以以高质量制造的二氧化硅，以及 与栅极和沟道中的所述一个接触的第二覆盖层。 覆盖层的介电常数高于第一层的介电常数，优选包括高<！ - SIPO

公开(公告)号：US07816727B2

公开(公告)日：2010-10-19

申请号：US12182318

申请日：2008-07-30

申请人： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

发明人： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

IPC分类号： H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28282 ,  G11C8/10 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

摘要翻译： 阻挡介电工程的电荷捕获存储单元包括电荷俘获元件，其通过阻挡电介质与栅极分离，所述阻挡电介质包括与电荷俘获元件接触的缓冲层，例如可以以高质量制造的二氧化硅，以及 与栅极和沟道中的所述一个接触的第二覆盖层。 覆盖层的介电常数高于第一层的介电常数，优选包括高<！ - SIPO

公开(公告)号：US07910981B2

公开(公告)日：2011-03-22

申请号：US11898528

申请日：2007-09-13

申请人： Sheng-Chih Lai ,  Hang-Ting Lue

发明人： Sheng-Chih Lai ,  Hang-Ting Lue

IPC分类号： H01L29/792

CPC分类号： H01L29/517 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.

摘要翻译： 提供了具有非易失性存储器的半导体器件及其制造方法。 半导体器件包括基底材料和堆叠结构。 设置在基材上的堆叠结构至少包括隧穿层，捕获层和电介质层。 捕获层设置在隧道层上。 电介质层具有介电常数并且设置在捕获层上。 当电介质层进行处理时，电介质层从第一固态转变为第二固态。