公开(公告)号：US08202779B2

公开(公告)日：2012-06-19

申请号：US12891310

申请日：2010-09-27

申请人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

发明人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/792

摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

摘要翻译： 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层 在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

公开(公告)号：US08384146B2

公开(公告)日：2013-02-26

申请号：US13428848

申请日：2012-03-23

申请人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

发明人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/792

摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

摘要翻译： 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层 在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

公开(公告)号：US20120056260A1

公开(公告)日：2012-03-08

申请号：US13294098

申请日：2011-11-10

申请人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

发明人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

IPC分类号： H01L29/792

CPC分类号： H01L27/11573 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11565 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

摘要翻译： 使用字线缩放的存储器和制造方法。 在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。 然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。 在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。 然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

公开(公告)号：US20100207191A1

公开(公告)日：2010-08-19

申请号：US12370950

申请日：2009-02-13

申请人： Shenqing FANG ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

发明人： Shenqing FANG ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L27/11573 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11565 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

摘要翻译： 使用字线缩放的存储器和制造方法。 在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。 然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。 在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。 然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

公开(公告)号：US08637918B2

公开(公告)日：2014-01-28

申请号：US13294098

申请日：2011-11-10

申请人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

发明人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

IPC分类号： H01L29/792

CPC分类号： H01L27/11573 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11565 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

摘要翻译： 使用字线缩放的存储器和制造方法。 在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。 然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。 在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。 然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

公开(公告)号：US08076199B2

公开(公告)日：2011-12-13

申请号：US12370950

申请日：2009-02-13

申请人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

发明人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

IPC分类号： H01L21/336

CPC分类号： H01L27/11573 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11565 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

摘要翻译： 使用字线缩放的存储器和制造方法。 在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。 然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。 在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。 然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

公开(公告)号：US20110221006A1

公开(公告)日：2011-09-15

申请号：US12722014

申请日：2010-03-11

申请人： Chun Chen ,  Shenqing Fang

发明人： Chun Chen ,  Shenqing Fang

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/11524 ,  H01L27/11521

摘要： An electronic device includes a substrate having isolation features defining active regions coextending over a surface of the substrate. The device also includes coextending line patterns crossing over the active regions, including string and ground selection lines and word lines between the string and ground selection lines. The device further includes first implant regions of a first conductivity type in the active regions between the word lines and having a first carrier concentration. The device further includes second implant regions of the first conductivity type in the active regions between edge ones of the word lines and an adjacent one of the string selection line and the ground selection line. In the device, the second implant region includes a low doping portion abutting the edge word lines and a high doping portion spaced from the edge word line by the low doping portion and having a second carrier concentration greater than the first carrier concentration.

摘要翻译： 电子器件包括具有限定在衬底的表面上共同延伸的有源区的隔离特征的衬底。 该装置还包括跨越有源区域的共同延伸的线图案，包括串和地选择线以及串和地选择线之间的字线。 该器件还包括位于字线之间的有源区中的第一导电类型的第一注入区，并具有第一载流子浓度。 该器件还包括第一导电类型的第二注入区域，位于字线的边缘之间的有源区和串选择线和地选择线中相邻的一个之间。 在器件中，第二注入区域包括邻接边缘字线的低掺杂部分和通过低掺杂部分与边缘字线间隔开的高掺杂部分，并且具有大于第一载流子浓度的第二载流子浓度。

公开(公告)号：US20110220981A1

公开(公告)日：2011-09-15

申请号：US12722083

申请日：2010-03-11

申请人： Chun Chen ,  Shenqing Fang

发明人： Chun Chen ,  Shenqing Fang

IPC分类号： H01L29/788 ,  H01L21/762

CPC分类号： H01L29/7853 ,  G11C16/0441 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76232 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7889

摘要： Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.

摘要翻译： 提供了制造电子设备及其电子设备的方法。 一种方法包括在衬底的半导体表面上形成一个或多个掩模层，并使用掩模层形成多个绝缘隔离特征和多个鳍式突起。 该方法还包括处理掩蔽层和多个鳍状突起，以为包括远侧延伸部分和近端基部的多个鳍状突起提供倒置的T形横截面。 该方法还包括在远端延伸部分上形成多个底栅层，并在多个绝缘隔离特征和多个底栅层上形成多个控制栅极层。

公开(公告)号：US08686492B2

公开(公告)日：2014-04-01

申请号：US12722083

申请日：2010-03-11

申请人： Chun Chen ,  Shenqing Fang

发明人： Chun Chen ,  Shenqing Fang

IPC分类号： H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7853 ,  G11C16/0441 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76232 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7889

摘要： Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.

公开(公告)号：US08441063B2

公开(公告)日：2013-05-14

申请号：US12982006

申请日：2010-12-30

申请人： Shenqing Fang ,  Tung-Sheng Chen ,  Chun Chen

发明人： Shenqing Fang ,  Tung-Sheng Chen ,  Chun Chen

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

摘要： A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.

摘要翻译： 存储器阵列包括多个位线和多个字线，栅极区域和电荷俘获层。 电荷捕获层比字线宽; 电荷捕获层延伸超过栅极区域的边缘以便于捕获和去除电荷。