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    Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure
    1.
    发明授权
    Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure 有权
    抛光后的金属/氧化物蚀刻，以防止半导体结构的相邻特征之间的桥接

    公开(公告)号：US07288487B1

    公开(公告)日：2007-10-30

    申请号：US11000870

    申请日：2004-12-01

    申请人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Calvin T. Gabriel

    发明人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Calvin T. Gabriel

    IPC分类号： H01L21/302

    CPC分类号： H01L21/02074 ,  H01L21/76819 ,  H01L21/7684

    摘要： Methods for eliminating and/or mitigating bridging and/or leakage caused by the contamination of a dielectric layer with fragments and/or residues of a conductive material are disclosed. The methods involve exposing a semiconductor substrate with a dielectric layer contaminated with fragments and/or residues of conductive materials to one or more conductor and/or dielectric etches. The disclosure by eliminating and/or mitigating metal bridging and/or leakage can provide one or more of the following advantages: high device reliability, decreased manufacturing cost, more efficient metallization, and increased performance.

    摘要翻译： 公开了用于消除和/或减轻由导电材料的碎片和/或残余物污染介电层引起的桥接和/或泄漏的方法。 所述方法包括将被污染有导电材料的碎片和/或残余物的介电层暴露于一个或多个导体和/或介电蚀刻物。 通过消除和/或减轻金属桥接和/或泄漏的公开可以提供一个或多个以下优点：高的器件可靠性，降低的制造成本，更有效的金属化和增加的性能。

    Memory device and method of simultaneous fabrication of core and periphery of same
    2.
    发明授权
    Memory device and method of simultaneous fabrication of core and periphery of same 有权
    同时制造芯片和周边的记忆装置和方法

    公开(公告)号：US07060564B1

    公开(公告)日：2006-06-13

    申请号：US10635089

    申请日：2003-08-06

    申请人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Weidong Qian ,  Kelwin King Wai Ko ,  Yu Sun

    发明人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Weidong Qian ,  Kelwin King Wai Ko ,  Yu Sun

    IPC分类号： H01L21/336

    CPC分类号： H01L27/105 ,  H01L27/11568 ,  H01L27/11573

    摘要： A method of fabricating a memory device having a core region of double-bit memory cells and a periphery region of logic circuitry includes forming a dielectric stack over the core and periphery areas of a semiconductor substrate and removing the dielectric stack from the periphery region. A gate dielectric is formed over the periphery area, followed by a first conductive layer over the core and periphery areas. After the formation and thermal processing of the gate dielectric, bitlines, which serve as source and drain regions, are implanted into the core area. Formation of the bitlines after the gate dielectric layer reduces lateral bitline diffusion and reduces short channel effects.

    摘要翻译： 一种制造具有双位存储器单元的核心区域和逻辑电路的外围区域的存储器件的方法包括在半导体衬底的芯部和外围区域上形成电介质堆叠并从外围区域去除电介质堆叠。 在外围区域上形成栅极电介质，随后在芯部和外围区域上形成第一导电层。 在栅极电介质的形成和热处理之后，用作源极和漏极区的位线被植入核心区域。 栅介质层之后的位线形成减少了横向位线扩散并减少了短沟道效应。

    METHOD AND DEVICE EMPLOYING POLYSILICON SCALING
    4.
    发明申请
    METHOD AND DEVICE EMPLOYING POLYSILICON SCALING 有权
    使用聚硅氧烷尺寸的方法和装置

    公开(公告)号：US20100207191A1

    公开(公告)日：2010-08-19

    申请号：US12370950

    申请日：2009-02-13

    申请人： Shenqing FANG ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

    发明人： Shenqing FANG ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

    IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/3205

    CPC分类号： H01L27/11573 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11565 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

    摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

    摘要翻译： 使用字线缩放的存储器和制造方法。 在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。 然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。 在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。 然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

    Recessed channel
    6.
    发明授权
    Recessed channel 有权
    嵌入渠道

    公开(公告)号：US06963108B1

    公开(公告)日：2005-11-08

    申请号：US10683631

    申请日：2003-10-10

    申请人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Jeff P. Erhardt ,  Emmanuil H. Lingunis

    发明人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Jeff P. Erhardt ,  Emmanuil H. Lingunis

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/04 ,  H01L29/78 ,  H01L29/792

    CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/045 ,  H01L29/66621 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/792

    摘要： A memory cell with reduced short channel effects is described. A trench region is formed in a semiconductor substrate. A source region and a drain region are formed on opposing sides of the trench region, wherein a bottom of the source region and a bottom of the drain region are above a floor of the trench region. A gate dielectric layer is formed in the trench region of the semiconductor substrate between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A control gate is formed on the semiconductor substrate above the recessed channel region, wherein the control gate is separated from the recessed channel region by the gate dielectric layer.

    摘要翻译： 描述了具有减小的短通道效应的存储单元。 在半导体衬底中形成沟槽区。 源极区域和漏极区域形成在沟槽区域的相对侧上，其中源极区域的底部和漏极区域的底部在沟槽区域的地板的上方。 在源极区域和漏极区域之间的半导体衬底的沟槽区域中形成栅极电介质层。 在沟槽区域，源极区域和漏极区域之下形成凹陷沟道区域。 控制栅极形成在凹陷沟道区域上方的半导体衬底上，其中控制栅极通过栅极介电层与凹陷沟道区分离。

    ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices
    7.
    发明授权
    ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices 有权
    ONO制造工艺，用于降低闪存器件底部氧化层中的氧空位

    公开(公告)号：US06803275B1

    公开(公告)日：2004-10-12

    申请号：US10308518

    申请日：2002-12-03

    申请人： Jaeyong Park ,  Hidehiko Shiraiwa ,  Arvind Halliyal ,  Jean Y. Yang ,  Inkuk Kang ,  Tazrien Kamal ,  Amir H. Jafarpour

    发明人： Jaeyong Park ,  Hidehiko Shiraiwa ,  Arvind Halliyal ,  Jean Y. Yang ,  Inkuk Kang ,  Tazrien Kamal ,  Amir H. Jafarpour

    IPC分类号： H01L21336

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L21/3144

    摘要： Process for fabricating a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on a semiconductor substrate, wherein the bottom oxide layer has a first oxygen vacancy content; treating the bottom oxide layer to decrease the first oxygen vacancy content to a second oxygen vacancy content; and depositing a dielectric charge-storage layer on the bottom oxide layer. In another embodiment, a process for fabricating a SONOS flash memory device includes forming a bottom oxide layer of an ONO structure on the semiconductor substrate under strongly oxidizing conditions, wherein the bottom oxide layer has a super-stoichiometric oxygen content and an oxygen vacancy content reduced relative to a bottom oxide layer formed by a conventional process; and depositing a dielectric charge-storage layer on the bottom oxide layer.

    摘要翻译： 在一个实施例中，包括在半导体衬底上形成ONO结构的底部氧化物层的SONOS闪速存储器件的制造方法，其中底部氧化物层具有第一氧空位含量; 处理底部氧化物层以将第一氧空位含量降低至第二氧空位含量; 以及在底部氧化物层上沉积介电电荷存储层。 在另一个实施例中，制造SONOS闪速存储器件的工艺包括在强氧化条件下在半导体衬底上形成ONO结构的底部氧化物层，其中底部氧化物层具有超化学计量的氧含量和氧空位含量降低 相对于通过常规方法形成的底部氧化物层; 以及在底部氧化物层上沉积介电电荷存储层。

    Method and device employing polysilicon scaling
    8.
    发明授权
    Method and device employing polysilicon scaling 有权
    采用多晶硅结垢的方法和装置

    公开(公告)号：US08637918B2

    公开(公告)日：2014-01-28

    申请号：US13294098

    申请日：2011-11-10

    申请人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

    发明人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11573 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11565 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

    摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

    摘要翻译： 使用字线缩放的存储器和制造方法。 在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。 然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。 在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。 然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

    SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same
    9.
    发明授权
    SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same 有权
    具有不均匀隧道氧化物的SONOS存储单元及其制造方法

    公开(公告)号：US08487373B2

    公开(公告)日：2013-07-16

    申请号：US12432441

    申请日：2009-04-29

    申请人： Shenqing Fang ,  Gang Xue ,  Wenmei Li ,  Inkuk Kang

    发明人： Shenqing Fang ,  Gang Xue ,  Wenmei Li ,  Inkuk Kang

    IPC分类号： H01L21/331

    CPC分类号： H01L29/792 ,  H01L27/11568 ,  H01L29/42352

    摘要： Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.

    摘要翻译： 公开了形成存储单元的方法。 一种方法包括在半导体衬底中形成源极 - 漏极结构，其中源极 - 漏极结构包括圆顶顶表面和侧壁表面。 在源极 - 漏极结构的顶壁和侧壁表面上形成氧化物层。 形成在源极 - 漏极结构的顶表面上的氧化物层的部分的厚度大于在源极 - 漏极结构的侧壁表面上形成的氧化物层的部分的厚度。

    Method and device employing polysilicon scaling
    10.
    发明授权
    Method and device employing polysilicon scaling 有权
    采用多晶硅结垢的方法和装置

    公开(公告)号：US08076199B2

    公开(公告)日：2011-12-13

    申请号：US12370950

    申请日：2009-02-13

    申请人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

    发明人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11573 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11565 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

    摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

    摘要翻译： 使用字线缩放的存储器和制造方法。 在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。 然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。 在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。 然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。