公开(公告)号：US08441063B2

公开(公告)日：2013-05-14

申请号：US12982006

申请日：2010-12-30

申请人： Shenqing Fang ,  Tung-Sheng Chen ,  Chun Chen

发明人： Shenqing Fang ,  Tung-Sheng Chen ,  Chun Chen

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

摘要： A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.

摘要翻译： 存储器阵列包括多个位线和多个字线，栅极区域和电荷俘获层。 电荷捕获层比字线宽; 电荷捕获层延伸超过栅极区域的边缘以便于捕获和去除电荷。

公开(公告)号：US09564331B2

公开(公告)日：2017-02-07

申请号：US13540373

申请日：2012-07-02

申请人： Shenqing Fang ,  Tung-Sheng Chen ,  Tim Thurgate ,  Di Li

发明人： Shenqing Fang ,  Tung-Sheng Chen ,  Tim Thurgate ,  Di Li

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L29/66 ,  H01L27/115 ,  H01L21/762

CPC分类号： H01L21/28282 ,  H01L21/76224 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.

摘要翻译： 一种用于在闪速存储器件中连续成形的电荷俘获层形成的方法和装置。 存储器件包括包括源/漏区的半导体层。 隔离区域邻近源极/漏极区域设置。 第一绝缘体设置在源极/漏极区域的上方。 电荷捕获层设置在第一绝缘体内，其中电荷捕获层包括主体部分和在所述主体部分的任一侧上的第一尖端和第二尖端，其中所述电荷捕获层延伸超过源极/漏极的宽度 地区。 第二绝缘体设置在电荷捕获层上方。 多晶硅栅极结构设置在第二绝缘体上方，其中所述控制栅极的宽度比所述源极/漏极区域的宽度宽。

公开(公告)号：US09412598B2

公开(公告)日：2016-08-09

申请号：US12973756

申请日：2010-12-20

申请人： Shenqing Fang ,  Tung-Sheng Chen

发明人： Shenqing Fang ,  Tung-Sheng Chen

IPC分类号： H01L21/336 ,  H01L21/3105 ,  H01L21/321 ,  H01L29/792 ,  H01L21/28 ,  H01L27/115 ,  H01L29/51

CPC分类号： H01L21/28282 ,  H01L21/28202 ,  H01L27/11568 ,  H01L29/518

摘要： Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners.

摘要翻译： 本技术的实施例针对场效应晶体管的栅极侧壁工程。 这些技术包括形成阻挡电介质区域和其表面的氮化。 在阻挡电介质区域的氮化之后，在其上形成栅极区域，并且栅极区域的侧壁被氧化以围绕栅极尖锐拐角并减小栅极拐角处的电场。

公开(公告)号：US08461053B2

公开(公告)日：2013-06-11

申请号：US12971818

申请日：2010-12-17

申请人： Tung-Sheng Chen ,  Shenqing Fang

发明人： Tung-Sheng Chen ,  Shenqing Fang

IPC分类号： H01L21/302

CPC分类号： H01L21/302 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

摘要： A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.

摘要翻译： 公开了一种用于双重图案化的方法。 在一个实施例中，通过在光致抗蚀剂图案的边缘周围放置间隔图案来开始在多个核心字线的任一侧上形成一对选择栅极字线。 将光致抗蚀剂图案剥离留下间隔图案。 修剪掩模放置在间隔图案的一部分上。 间隔图案的部分被蚀刻掉，不被修剪掩模覆盖。 去除修剪掩模，其中间隔图案的第一剩余部分限定多个核心字线。 放置焊盘掩模，使得焊盘掩模和间隔物图案的第二剩余部分在多个核心字线的任一侧上限定选择栅极字线。 最后，通过使用激光掩模和间隔物图案的第一和第二剩余部分来蚀刻至少一个图案转印层，以将选择栅极字线和多个核心字线蚀刻成多晶硅层。

公开(公告)号：US08263458B2

公开(公告)日：2012-09-11

申请号：US12973631

申请日：2010-12-20

申请人： Tung-Sheng Chen ,  Shenqing Fang

发明人： Tung-Sheng Chen ,  Shenqing Fang

IPC分类号： H01L21/336

CPC分类号： H01L21/76232 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/792

摘要： Embodiments of the present technology are directed toward charge trapping region process margin engineering for charge trapping field effect transistor. The techniques include forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount. A portion of the substrate is oxidized to form a tunneling dielectric region. A first set of one or more nitride layers are deposited on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount that the tops of the shallow trench isolation regions extend above the substrate. A portion of the first set of nitride layers is etched back to the tops of the trench isolation regions. A second set of one or more nitride layers is deposited on the etched back first set of nitride layers. The second set of nitride layers is oxidized to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region. A gate region is then deposited on the blocking dielectric region.

摘要翻译： 本技术的实施例针对电荷捕获场效应晶体管的电荷捕获区域工艺裕度工程。 这些技术包括在衬底上形成多个浅沟槽隔离区域，其中浅沟槽隔离区域的顶部在衬底上延伸给定量。 衬底的一部分被氧化以形成隧道电介质区域。 第一组一个或多个氮化物层沉积在隧道电介质区域和浅沟槽隔离区域上，其中第一组氮化物层的厚度大约为给定量的一半，即浅沟槽隔离区的顶部在上面延伸 底物。 第一组氮化物层的一部分被回蚀刻到沟槽隔离区的顶部。 在蚀刻后的第一组氮化物层上沉积第二组一个或多个氮化物层。 第二组氮化物层被氧化以在隧穿电介质区域上形成电荷俘获区域，并在电荷俘获区域上形成阻挡电介质区域。 然后将栅极区域沉积在阻挡电介质区域上。

公开(公告)号：US08686492B2

公开(公告)日：2014-04-01

申请号：US12722083

申请日：2010-03-11

申请人： Chun Chen ,  Shenqing Fang

发明人： Chun Chen ,  Shenqing Fang

IPC分类号： H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7853 ,  G11C16/0441 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76232 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7889

摘要： Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.

公开(公告)号：US08598646B2

公开(公告)日：2013-12-03

申请号：US13006339

申请日：2011-01-13

申请人： Chun Chen ,  Shenqing Fang

发明人： Chun Chen ,  Shenqing Fang

IPC分类号： H01L27/105

CPC分类号： H01L21/28282 ,  H01L21/76224 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66833

摘要： An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.

摘要翻译： 一种电子器件包括具有半导体表面的衬底，具有通过存储单元区域和选择栅极区域沿第一方向共同延伸的多个鳍式突起。 电子设备还包括设置在突起之间的空间中的电介质隔离材料。 在电子设备中，存储单元区域中的介质隔离材料的高度小于存储单元区域中的突起的高度，并且选择栅极区域中的介电隔离材料的高度大于或等于 突起在选择栅极区域的高度。 电子设备还包括设置在存储单元区域内的衬底上的栅极特征以及突出部分和介电隔离材料上的选择栅极区域，其中栅极特征在横向于第一方向的第二方向上共同延伸。

公开(公告)号：US08637918B2

公开(公告)日：2014-01-28

申请号：US13294098

申请日：2011-11-10

申请人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

发明人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

IPC分类号： H01L29/792

CPC分类号： H01L27/11573 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11565 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

摘要翻译： 使用字线缩放的存储器和制造方法。 在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。 然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。 在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。 然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

公开(公告)号：US08202779B2

公开(公告)日：2012-06-19

申请号：US12891310

申请日：2010-09-27

申请人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

发明人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/792

摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

摘要翻译： 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层 在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

公开(公告)号：US08076199B2

公开(公告)日：2011-12-13

申请号：US12370950

申请日：2009-02-13

申请人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

发明人： Shenqing Fang ,  Chun Chen ,  Wenmei Li ,  Inkuk Kang ,  Gang Xue ,  Hyesook Hong

IPC分类号： H01L21/336

CPC分类号： H01L27/11573 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11565 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

摘要翻译： 使用字线缩放的存储器和制造方法。 在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。 然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。 在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。 然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。