Power-saving network apparatus having physical layer circuit capable of entering low power state
    1.
    发明授权
    Power-saving network apparatus having physical layer circuit capable of entering low power state 有权
    具有能够进入低功率状态的物理层电路的省电网络装置

    公开(公告)号:US08326975B2

    公开(公告)日:2012-12-04

    申请号:US12354786

    申请日:2009-01-16

    IPC分类号: G06F15/16 G06F1/26 G06F1/32

    CPC分类号: G06F1/3209 H04L69/323

    摘要: A power-saving network apparatus includes a MAC and a PHY. The PHY includes a transmitter and a receiver. The transmitter executes the operations of: transmitting a data signal to a remote network apparatus according to output packets of the MAC when the transmitter enters a normal state; transmitting an idle signal to the remote network apparatus when the transmitter enters an idle state; transmitting an indication signal to the remote network apparatus to notify it to enter a low power state, wherein the indication signal is different from the idle signal; entering the idle state or the normal state from the low power state in response to at least one of a predetermined period and a transmitting enable signal.

    摘要翻译: 省电网络装置包括MAC和PHY。 PHY包括发射机和接收机。 发射机执行以下操作:当发射机进入正常状态时,根据MAC的输出分组向远程网络设备发送数据信号; 当发射机进入空闲状态时,向远程网络设备发送空闲信号; 向所述远程网络装置发送指示信号以通知其进入低功率状态,其中所述指示信号与所述空闲信号不同; 响应于预定周期和发送使能信号中的至少一个,从低功率状态进入空闲状态或正常状态。

    POWER-SAVING NETWORK APPARATUS AND METHOD THEREOF
    2.
    发明申请
    POWER-SAVING NETWORK APPARATUS AND METHOD THEREOF 有权
    节电网络装置及其方法

    公开(公告)号:US20090193109A1

    公开(公告)日:2009-07-30

    申请号:US12354786

    申请日:2009-01-16

    IPC分类号: G06F15/16 G06F1/32

    CPC分类号: G06F1/3209 H04L69/323

    摘要: A power-saving network apparatus includes a MAC and a PHY. The PHY includes a transmitter and a receiver. The transmitter executes the operations of: transmitting a data signal to a remote network apparatus according to output packets of the MAC when the transmitter enters a normal state; transmitting an idle signal to the remote network apparatus when the transmitter enters an idle state; transmitting an indication signal to the remote network apparatus to notify it to enter a low power state, wherein the indication signal is different from the idle signal; entering the idle state or the normal state from the low power state in response to at least one of a predetermined period and a transmitting enable signal.

    摘要翻译: 省电网络装置包括MAC和PHY。 PHY包括发射机和接收机。 发射机执行以下操作:当发射机进入正常状态时,根据MAC的输出分组向远程网络设备发送数据信号; 当发射机进入空闲状态时,向远程网络设备发送空闲信号; 向所述远程网络装置发送指示信号以通知其进入低功率状态,其中所述指示信号与所述空闲信号不同; 响应于预定周期和发送使能信号中的至少一个,从低功率状态进入空闲状态或正常状态。

    Network processor and energy saving method thereof
    3.
    发明授权
    Network processor and energy saving method thereof 有权
    网络处理器及其节能方法

    公开(公告)号:US09122479B2

    公开(公告)日:2015-09-01

    申请号:US12060356

    申请日:2008-04-01

    IPC分类号: G06F1/32

    摘要: A network processor includes a transceiver circuit, a network data processing unit, and a clock signal control unit. The transceiver circuit transmits and receives a network signal, compares a voltage level of the network signal with a threshold value, outputs a comparison result, and operates under a first clock signal. The network data processing unit is coupled to the transceiver circuit to process the network signal, and operates under a second clock signal different from the first clock signal. The clock signal control unit disables supply of the second clock signal to the network data processing unit when the voltage level is smaller than the threshold value, and enables supply of the second clock signal to the network data processing unit when the voltage level is not smaller than the threshold value. An energy saving method for a network processor is also disclosed.

    摘要翻译: 网络处理器包括收发器电路,网络数据处理单元和时钟信号控制单元。 收发电路发送和接收网络信号,将网络信号的电压电平与阈值进行比较,输出比较结果,并在第一时钟信号下工作。 网络数据处理单元耦合到收发器电路以处理网络信号,并在与第一时钟信号不同的第二时钟信号下工作。 当电压电平小于阈值时,时钟信号控制单元禁止向网络数据处理单元提供第二时钟信号,并且当电压电平不小于时能够向网络数据处理单元提供第二时钟信号 超过阈值。 还公开了一种用于网络处理器的节能方法。

    NETWORK PROCESSOR AND ENERGY SAVING METHOD THEREOF
    4.
    发明申请
    NETWORK PROCESSOR AND ENERGY SAVING METHOD THEREOF 有权
    网络处理器及其节能方法

    公开(公告)号:US20080250258A1

    公开(公告)日:2008-10-09

    申请号:US12060356

    申请日:2008-04-01

    IPC分类号: G06F1/32

    摘要: A network processor includes a transceiver circuit, a network data processing unit, and a clock signal control unit. The transceiver circuit transmits and receives a network signal, compares a voltage level of the network signal with a threshold value, outputs a comparison result, and operates under a first clock signal. The network data processing unit is coupled to the transceiver circuit to process the network signal, and operates under a second clock signal different from the first clock signal. The clock signal control unit disables supply of the second clock signal to the network data processing unit when the voltage level is smaller than the threshold value, and enables supply of the second clock signal to the network data processing unit when the voltage level is not smaller than the threshold value. An energy saving method for a network processor is also disclosed.

    摘要翻译: 网络处理器包括收发器电路,网络数据处理单元和时钟信号控制单元。 收发电路发送和接收网络信号,将网络信号的电压电平与阈值进行比较,输出比较结果,并在第一时钟信号下工作。 网络数据处理单元耦合到收发器电路以处理网络信号,并在与第一时钟信号不同的第二时钟信号下工作。 当电压电平小于阈值时,时钟信号控制单元禁止向网络数据处理单元提供第二时钟信号,并且当电压电平不小于时能够向网络数据处理单元提供第二时钟信号 超过阈值。 还公开了一种用于网络处理器的节能方法。

    Ethernet system and related clock synchronization method
    5.
    发明授权
    Ethernet system and related clock synchronization method 有权
    以太网系统及相关时钟同步方法

    公开(公告)号:US08284794B2

    公开(公告)日:2012-10-09

    申请号:US12629897

    申请日:2009-12-03

    IPC分类号: H04J15/00

    CPC分类号: G06F1/12

    摘要: A master device for an Ethernet system is disclosed. The master device includes a receiver, a buffer, a phase lock loop unit, and a transmitter. The receiver is used for generating phase adjustment data according to transmission data sent by a slave device when the master device operates during a switch mode. The buffer is coupled to the receiver for accumulating the phase adjustment data and outputting a phase adjustment value. The phase lock loop unit is coupled to the buffer for adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock. The transmitter is used for transmitting initialization data to the slave device according to the output clock.

    摘要翻译: 公开了一种用于以太网系统的主设备。 主设备包括接收器,缓冲器,锁相环单元和发射器。 当主设备在切换模式期间操作时,接收机用于根据从设备发送的传输数据来生成相位调整数据。 缓冲器耦合到接收器,用于累加相位调整数据并输出相位调整值。 锁相环单元耦合到缓冲器,用于根据相位调整值调节输出时钟的相位,以保持恢复时钟和输出时钟之间的固定相位差。 发射机用于根据输出时钟将初始化数据发送到从设备。

    Ethernet System and Related Clock Synchronization Method
    6.
    发明申请
    Ethernet System and Related Clock Synchronization Method 有权
    以太网系统和相关时钟同步方法

    公开(公告)号:US20100169704A1

    公开(公告)日:2010-07-01

    申请号:US12629897

    申请日:2009-12-03

    IPC分类号: G06F13/00 G06F11/07 G06F1/12

    CPC分类号: G06F1/12

    摘要: A master device for an Ethernet system is disclosed. The master device includes a receiver, a buffer, a phase lock loop unit, and a transmitter. The receiver is used for generating phase adjustment data according to transmission data sent by a slave device when the master device operates during a switch mode. The buffer is coupled to the receiver for accumulating the phase adjustment data and outputting a phase adjustment value. The phase lock loop unit is coupled to the buffer for adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock. The transmitter is used for transmitting initialization data to the slave device according to the output clock.

    摘要翻译: 公开了一种用于以太网系统的主设备。 主设备包括接收器,缓冲器,锁相环单元和发射器。 当主设备在切换模式期间操作时,接收机用于根据从设备发送的传输数据来生成相位调整数据。 缓冲器耦合到接收器,用于累加相位调整数据并输出相位调整值。 锁相环单元耦合到缓冲器,用于根据相位调整值调节输出时钟的相位,以保持恢复时钟和输出时钟之间的固定相位差。 发射机用于根据输出时钟将初始化数据发送到从设备。

    Microelectronic device and pin arrangement method thereof
    7.
    发明申请
    Microelectronic device and pin arrangement method thereof 有权
    微电子器件及其引脚排列方法

    公开(公告)号:US20090106611A1

    公开(公告)日:2009-04-23

    申请号:US12287831

    申请日:2008-10-14

    IPC分类号: G01R31/3177 G06F11/25

    摘要: The present invention provides a microelectronic device with a circuit core and a boundary scan test interface sharing a number of pre-selected pins. In the mode of a boundary scan test, the boundary scan test interface manipulates the input and output of the test signal through the shared pins. Pins necessary for the microelectronic device are therefore reduced.

    摘要翻译: 本发明提供一种具有电路核心和共享多个预先选择的引脚的边界扫描测试接口的微电子器件。 在边界扫描测试模式下,边界扫描测试界面通过共享引脚操作测试信号的输入和输出。 因此,微电子器件所需的引脚减少。

    METHOD FOR DETERMINING CONNECTION STATUS OF WIRED NETWORK
    8.
    发明申请
    METHOD FOR DETERMINING CONNECTION STATUS OF WIRED NETWORK 有权
    用于确定有线网络连接状态的方法

    公开(公告)号:US20070211643A1

    公开(公告)日:2007-09-13

    申请号:US11682889

    申请日:2007-03-07

    IPC分类号: H04J1/16 H04L12/66

    摘要: A method applied to a wired network including a first network device and a second network device is disclosed. The first and second network devices each include a first set of connection ends and a second set of connection ends. Firstly, the first network device transmits a specific signal pattern through its first set and second set of connection ends. Then, the first network device detects whether a signal is received at its first set and second set of connection ends. If it is determined that a signal is not received at the first set connection ends while a signal is received at the second set connection ends, the first network device determines that its second set of connection ends is not correctly coupled to the second set of connection ends of the second network device.

    摘要翻译: 公开了一种应用于包括第一网络设备和第二网络设备的有线网络的方法。 第一和第二网络设备各自包括第一组连接端和第二组连接端。 首先,第一网络设备通过其第一组和第二组连接端发送特定信号模式。 然后,第一网络设备检测在其第一组和第二组连接结束时是否接收到信号。 如果在第二设定连接处接收到信号时确定在第一设定连接处没有接收到信号,则第一网络设备确定其第二组连接端没有正确地耦合到第二组连接 第二网络设备的端点。

    Order adaptive finite impulse response filter and operating method thereof
    9.
    发明授权
    Order adaptive finite impulse response filter and operating method thereof 有权
    自适应有限脉冲响应滤波器及其操作方法

    公开(公告)号:US08285772B2

    公开(公告)日:2012-10-09

    申请号:US12322503

    申请日:2009-02-03

    IPC分类号: G06F17/10

    CPC分类号: H03H17/0294 H03H21/0012

    摘要: A device for allocating a number of taps of a designated finite impulse response filter is disclosed. The device comprises a plurality of designated finite impulse response filters having fixed number of taps, a plurality of allocation finite impulse response filters having fixed number of taps, a control unit and an estimate unit. Depending on intensities of responses to interferences, at least one of the allocation FIR filters may be coupled in series to any one of the designated finite impulse response filters, thereby to provide a signal having excellent quality.

    摘要翻译: 公开了一种用于分配指定的有限脉冲响应滤波器的抽头的装置。 该装置包括具有固定数量的抽头的多个指定的有限脉冲响应滤波器,具有固定数量的抽头的多个分配有限脉冲响应滤波器,控制单元和估计单元。 根据对干扰的响应的强度,分配FIR滤波器中的至少一个可以与指定的有限脉冲响应滤波器中的任何一个串联耦合,从而提供具有优良品质的信号。

    METHOD FOR GENERATING A SPREAD SPECTRUM CLOCK AND APPARATUS THEREOF
    10.
    发明申请
    METHOD FOR GENERATING A SPREAD SPECTRUM CLOCK AND APPARATUS THEREOF 有权
    用于产生传播频谱时钟的方法及其装置

    公开(公告)号:US20090190631A1

    公开(公告)日:2009-07-30

    申请号:US12358261

    申请日:2009-01-23

    IPC分类号: H04B1/69

    CPC分类号: H04B1/69 G06F1/04

    摘要: A method for generating a spread spectrum clock includes the steps of providing a reference clock having a reference period; generating a plurality of output clocks respectively having different phases according to the reference clock; generating a first/second control signal according to the reference clock and a spread spectrum clock and starting a first/second duration accordingly; during the first/second duration, outputting a first/second selecting signal representing a first/second predetermined sequence according to the first/second control signal, wherein the second predetermined sequence is a substantial reversed sequence of the first predetermined sequence; and during the first/second duration, sequentially outputting some or all of the output clocks as the spread spectrum clock according to the first/second predetermined sequence.

    摘要翻译: 一种用于产生扩频时钟的方法包括以下步骤:提供具有参考周期的参考时钟; 根据参考时钟产生分别具有不同相位的多个输出时钟; 根据参考时钟和扩频时钟产生第一/第二控制信号并相应地开始第一/第二持续时间; 在第一/第二持续时间期间,根据第一/第二控制信号输出表示第一/第二预定序列的第一/第二选择信号,其中第二预定序列是第一预定序列的实质上相反的顺序; 并且在第一/第二持续时间期间,根据第一/第二预定序列顺序地输出部分或全部输出时钟作为扩频时钟。