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1.发明授权Arithmetic method and function arithmetic circuit for a fast fourier transform 失效用于快速傅里叶变换的算术方法和函数运算电路公开(公告)号：US07634524B2
公开(公告)日：2009-12-15
申请号：US10823570
申请日：2004-04-14
IPC分类号： G06F1/02
CPC分类号： G06F17/142
摘要： A cyclic equation setting unit transforms and sets a Taylor series equation for calculating a sine function into a single cyclic equation common to terms of the Taylor series equation, the single cyclic equation having a new known number Q that is defined by multiplying a known number Q and the square of a variable X, shifting the result by a shift number S and then adding a constant K thereto. An adjustment unit adjusts and prepares the shift number S such that within a variation range of the variable X the variable X has a maximum value 1 with the constant K being not greater than 1. A cyclic equation executing unit inputs and converts angle information i to the variable X, and executing the cyclic equation in sequence from higher order term to lower order term for the number of terms of the Taylor series equation to derive a sine function of the angle information i.
摘要翻译： 循环方程设置单元将用于计算正弦函数的泰勒级数方程转换并设置为与泰勒级数方程式相同的单个循环方程，具有新的已知数Q的单个循环方程式通过将已知数量Q 和变量X的平方，将结果移位移位数S，然后向其中加上常数K. 调整单元调整并准备移位号S，使得在变量X的变化范围内，变量X具有常数K不大于1的最大值1.循环方程执行单元输入并转换角度信息i至 变量X，并且对于泰勒级数方程的项数，从高阶项到低阶项顺序执行循环方程，以导出角度信息i的正弦函数。
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公开(公告)号：US07461114B2
公开(公告)日：2008-12-02
申请号：US10645498
申请日：2003-08-22
IPC分类号： G06F15/00
CPC分类号： G06F17/142
摘要： A Fourier transform apparatus whose pipeline width is independent of transform point number of individual pipeline FFT circuits in each stage and composed of a preceding stage and a succeeding stage. Each of the stages includes M(power of 2)-point radix 2 pipeline FFT circuits each having two-parallel inputs/outputs in a number of a (divisor of M) which are equal in respect to the transform point number and data permutating means for data supply to the transform means of each stage so that the pipeline width of the Fourier transform apparatus is made independent of the transform point numbers of the individual pipeline FFT circuits in each stage.
摘要翻译： 一个傅立叶变换装置，其管线宽度与每个阶段各个管线FFT电路的转换点数无关，由前一级和后一级组成。 每个级包括M个（2个）点2个流水线FFT电路，每个具有两个对于转换点号相等的（除数为M）的并行输入/输出，并且数据排列装置 用于将数据提供给每个级的变换装置，使得傅立叶变换装置的管线宽度独立于每个级中各个管线FFT电路的变换点号。
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公开(公告)号：US06938191B2
公开(公告)日：2005-08-30
申请号：US10103787
申请日：2002-03-25
申请人： Keiji Sato , Toshiro Nakazuru , Shigeaki Okutani , Noboru Morita
发明人： Keiji Sato , Toshiro Nakazuru , Shigeaki Okutani , Noboru Morita
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/00 , G06F11/22
CPC分类号： G01R31/318555 , G01R31/318572
摘要： The present invention provides an access control device and a testing method that can simplify the software operations in an access control operation such as a JTAG control operation, and enable the hardware to perform a high-speed control operation. The access control device conducts a test or diagnosis on an object by accessing a serial interface based on a command and data that specify a testing or diagnosing route. Under the control of a processor, a control circuit in the access control device executes an access sequence in accordance with a command string and an input data string stored in a memory, and stores the data outputted from the object to be tested or diagnosed in the memory as an output data string. The control circuit sets a state transition route for each objective state in advance, so that a transition route can be readily determined for an objective state specified by the command string.
摘要翻译： 本发明提供一种访问控制装置和测试方法，其可以简化诸如JTAG控制操作之类的访问控制操作中的软件操作，并且使硬件能够执行高速控制操作。 访问控制设备通过基于指定测试或诊断路由的命令和数据访问串行接口来对对象进行测试或诊断。 在处理器的控制下，访问控制装置中的控制电路根据存储在存储器中的命令串和输入数据串执行访问序列，并将从被测试对象或被诊断的对象输出的数据存储在 内存作为输出数据串。 控制电路预先为每个目标状态设置状态转移路径，使得可以容易地确定由命令串指定的目标状态的转换路线。
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公开(公告)号：US07620676B2
公开(公告)日：2009-11-17
申请号：US11346581
申请日：2006-02-03
IPC分类号： G06F7/50
CPC分类号： G06F1/0356
摘要： Input data is divided into a plurality of blocks, and the blocks are corresponded to each address of the lookup table, and a block is divided into a plurality of sections according to the change of the output data, and at this time position information to indicates the boundary of the section, and output data in each section are stored in an address corresponding to each block, so that the memory capacity required for the lookup table can be decreased.
摘要翻译： 输入数据被分成多个块，并且这些块对应于查找表的每个地址，并且根据输出数据的改变将块划分成多个部分，并且此时位置信息指示 该部分的边界和每个部分中的输出数据被存储在与每个块对应的地址中，从而可以减少查找表所需的存储器容量。
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公开(公告)号：US20060190515A1
公开(公告)日：2006-08-24
申请号：US11346581
申请日：2006-02-03
IPC分类号： G06F1/02
CPC分类号： G06F1/0356
摘要： Input data is divided into a plurality of blocks, and the blocks are corresponded to each address of the lookup table, and a block is divided into a plurality of sections according to the change of the output data, and at this time position information to indicates the boundary of the section, and output data in each section are stored in an address corresponding to each block, so that the memory capacity required for the lookup table can be decreased.
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公开(公告)号：US20050131975A1
公开(公告)日：2005-06-16
申请号：US10823570
申请日：2004-04-14
CPC分类号： G06F17/142
摘要： A cyclic equation setting unit transforms and sets a Taylor series equation for calculating a sine function into a single cyclic equation common to terms of the Taylor series equation, the single cyclic equation having a new known number Q that is defined by multiplying a known number Q and the square of a variable X, shifting the result by a shift number Sand then adding a constant K thereto. An adjustment unit adjusts and prepares the shift number S such that within a variation range of the variable X the variable X has a maximum value 1 with the constant K being not greater than 1. A cyclic equation executing unit inputs and converts angle information i to the variable X, and executing the cyclic equation in sequence from higher order term to lower order term for the number of terms of the Taylor series equation to derive a sine function of the angle information i.
摘要翻译： 循环方程设置单元将用于计算正弦函数的泰勒级数方程转换并设置为与泰勒级数方程式相同的单个循环方程，具有新的已知数Q的单个循环方程式通过将已知数量Q 和变量X的平方，将结果移位移位数Sand，然后向其中加上常数K。 调整单元调整并准备移位号S，使得在变量X的变化范围内，变量X具有常数K不大于1的最大值1.循环方程执行单元输入并转换角度信息i至 变量X，并且对于泰勒级数方程的项数，从高阶项到低阶项顺序执行循环方程，以导出角度信息i的正弦函数。
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公开(公告)号：US5959862A
公开(公告)日：1999-09-28
申请号：US390223
申请日：1995-02-16
CPC分类号： G06F5/00 , H04L25/0262 , H04L25/03834
摘要： When the number of pieces of data which are operated on by an operation unit per unit time is N times the number of pieces of data entered into a data entry section per unit time and the operation unit performs an operation on a data set consisting of K samples of data, the data set extraction starting positions on a data string entered into the data entry section are shifted by K/N samples. Each of data sets thus extracted from the data string is sent to the operation unit to be operated on. This configuration permits the precision of operations by the operation unit to be improved according to the ratio K/N without reducing the operation efficiency of the operation unit.
摘要翻译： 当每单位时间由操作单元操作的数据数量是每单位时间输入到数据输入部分的数据数量的N倍，并且操作单元对由K组成的数据集执行操作 将数据样本数据输入到数据输入部分的数据串上的数据集提取开始位置移位K / N个样本。 从数据串中提取的每个数据集被发送到操作单元。 该配置允许在不降低操作单元的操作效率的情况下，根据比率K / N来提高操作单元的操作精度。
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8.发明授权Information processing apparatus including synchronous storage having backup registers for storing the latest sets of information to enable state restoration after interruption 失效信息处理设备包括具有用于存储最新信息集的备份寄存器的同步存储器，以使得能够在中断之后恢复状态
公开(公告)号：US5701436A
公开(公告)日：1997-12-23
申请号：US508685
申请日：1995-07-28
CPC分类号： G06F11/141
摘要： Herein disclosed is an information processing apparatus having a synchronous storage and the synchronous storage which can resume an operation continuing from before an interruption without hindrance even after a series of read/write operations have been interrupted and a read/write of internal condition values has been performed in a scanning operation or the like. The information processing apparatus successively selects information stored in address backup registers in two stages and data backup registers in two stages and outputs the selected information to the synchronous storage when a normal operation is resumed, thereby restoring an address data register, a data input register and a data output register to the same conditions as before the interruption of the normal operation. This invention is applicable to a synchronous storage accessible in synchronism with a system clock and an information processing apparatus having such synchronous storage.
摘要翻译： 这里公开的是具有同步存储和同步存储的信息处理装置，即使在一系列读/写操作已被中断并且内部条件值的读/写已经被 在扫描操作等中执行。 信息处理装置在两级依次选择存储在地址备份寄存器中的信息和两级的数据备份寄存器，当恢复正常操作时，将选择的信息输出到同步存储器，从而恢复地址数据寄存器，数据输入寄存器和 一个数据输出寄存器的状态与之前中断的正常操作相同。 本发明适用于与系统时钟同步访问的同步存储器和具有这种同步存储器的信息处理装置。
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9.发明授权
公开(公告)号：US4507728A
公开(公告)日：1985-03-26
申请号：US356468
申请日：1982-03-09
CPC分类号： G06F15/8076 , G06F9/30 , G06F9/3885
摘要： The present invention is a data processing system which has plural operation units which can execute plural instructions in parallel. The system also has plural instruction control units each of which comprises at least two stages, one for reading source operands from a local storage, and another for writing a resultant operand into the local storage. Each instruction control unit is provided with specific bank timing signals for accessing the local storage.
摘要翻译： 本发明是一种数据处理系统，其具有可并行执行多个指令的多个操作单元。 该系统还具有多个指令控制单元，每个指令控制单元包括至少两个级，一个用于从本地存储器读取源操作数，另一级用于将合成的操作数写入本地存储器。 每个指令控制单元被提供有用于访问本地存储器的特定存储体定时信号。
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10.发明授权Bank interleaved vector processor having a fixed relationship between start timing signals 失效银行交错向量处理器在开始定时信号之间具有固定的关系
公开(公告)号：US4435765A
公开(公告)日：1984-03-06
申请号：US322717
申请日：1981-11-18
CPC分类号： G06F15/8076
摘要： The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational processing unit, the desired data is transferred to the vector registers from the main memory unit and is held therein, and various processings such as a logical operation are carried out by sequentially accessing the elements within said vector registers. The present invention also includes a plurality of memory banks which can be independently accessed and are provided for the vector registers. A series of elements of each vector register are interleaved in the plurality of memory banks and the elements having the same numbering in each vector register are arranged in the same memory bank. Timing necessary for starting access to a series of elements of said vector registers are specified for each class of processing, so that the vector operation processings can be done very effectively and without operand collision.
摘要翻译： 本发明公开了一种数据处理系统，其中在主存储器单元和操作处理单元之间提供由多个元件组成的多个向量寄存器，所需数据从主存储器单元传送到矢量寄存器并保持在其中 ，并且通过顺序访问所述向量寄存器内的元素来执行诸如逻辑操作的各种处理。 本发明还包括多个存储体，其可以被独立地访问并被提供给矢量寄存器。 每个向量寄存器的一系列元素在多个存储体中交错，并且在每个向量寄存器中具有相同编号的元件被布置在同一存储体中。 为每一类处理指定开始访问所述向量寄存器的一系列元素所必需的定时，使得矢量操作处理可以非常有效地进行而不具有操作数冲突。
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