公开(公告)号：US08854869B2

公开(公告)日：2014-10-07

申请号：US12855691

申请日：2010-08-12

申请人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

发明人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C5/06 ,  G11C11/413

CPC分类号： G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

摘要翻译： 提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。 半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。 多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。 具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。 一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。 一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。

公开(公告)号：US20110063895A1

公开(公告)日：2011-03-17

申请号：US12855691

申请日：2010-08-12

申请人： Shigenobu KOMATSU ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

发明人： Shigenobu KOMATSU ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

IPC分类号： G11C11/417 ,  G11C11/412 ,  G11C5/14

CPC分类号： G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

摘要翻译： 提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。 半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。 多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。 具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。 一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。 一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。

公开(公告)号：US08125845B2

公开(公告)日：2012-02-28

申请号：US12687339

申请日：2010-01-14

申请人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki

发明人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki

IPC分类号： G11C7/00

CPC分类号： G11C11/413 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227

摘要： Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.

摘要翻译： 即使使用复制位线的存储器的存储器容量更高，读出放大器使能信号的产生定时的波动也减小。 半导体集成电路器件包括多个字线，多个位线，多个普通存储器单元，访问控制电路，多个读出放大器，第一和第二复制位线，第一和第二复制 存储单元，以及第一和第二逻辑电路。 第一和第二复制存储器单元分别连接到第一和第二复制位线; 第一和第二逻辑电路的输入分别连接到第一和第二复制位线; 从第二逻辑电路的输出产生读出放大器使能信号; 并且该信号被提供给多个感测放大器。

公开(公告)号：US20100177580A1

公开(公告)日：2010-07-15

申请号：US12687339

申请日：2010-01-14

申请人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki

发明人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki

IPC分类号： G11C7/00 ,  G11C7/02

CPC分类号： G11C11/413 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227

摘要： Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.

摘要翻译： 即使使用复制位线的存储器的存储器容量更高，读出放大器使能信号的产生定时的波动也减小。 半导体集成电路器件包括多个字线，多个位线，多个普通存储器单元，访问控制电路，多个读出放大器，第一和第二复制位线，第一和第二复制 存储单元，以及第一和第二逻辑电路。 第一和第二复制存储器单元分别连接到第一和第二复制位线; 第一和第二逻辑电路的输入分别连接到第一和第二复制位线; 从第二逻辑电路的输出产生读出放大器使能信号; 并且该信号被提供给多个感测放大器。

公开(公告)号：US20060274571A1

公开(公告)日：2006-12-07

申请号：US11504077

申请日：2006-08-15

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

公开(公告)号：US07715223B2

公开(公告)日：2010-05-11

申请号：US12314190

申请日：2008-12-05

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nll

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nll

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

公开(公告)号：US20060056229A1

公开(公告)日：2006-03-16

申请号：US11127286

申请日：2005-05-12

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

摘要翻译： 本发明提供一种具有SRAM的半导体集成电路器件，其具有满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

公开(公告)号：US20120044775A1

公开(公告)日：2012-02-23

申请号：US13317846

申请日：2011-10-31

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C7/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

公开(公告)号：US20100188887A1

公开(公告)日：2010-07-29

申请号：US12662029

申请日：2010-03-29

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

公开(公告)号：US08441843B2

公开(公告)日：2013-05-14

申请号：US13317846

申请日：2011-10-31

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.