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公开(公告)号：US08854869B2
公开(公告)日：2014-10-07
申请号：US12855691
申请日：2010-08-12
申请人： Shigenobu Komatsu , Masanao Yamaoka , Noriaki Maeda , Masao Morimoto , Yasuhisa Shimazaki , Yasuyuki Okuma , Toshiaki Sano
发明人： Shigenobu Komatsu , Masanao Yamaoka , Noriaki Maeda , Masao Morimoto , Yasuhisa Shimazaki , Yasuyuki Okuma , Toshiaki Sano
IPC分类号： G11C11/00 , G11C5/14 , G11C5/06 , G11C11/413
CPC分类号： G11C11/417 , G11C5/06 , G11C5/14 , G11C11/413 , H01L27/092 , H01L27/1104
摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.
摘要翻译： 提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。 半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。 多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。 具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。 一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。 一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。
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公开(公告)号：US08125845B2
公开(公告)日：2012-02-28
申请号：US12687339
申请日：2010-01-14
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C7/08 , G11C7/22 , G11C7/227
摘要： Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.
摘要翻译： 即使使用复制位线的存储器的存储器容量更高，读出放大器使能信号的产生定时的波动也减小。 半导体集成电路器件包括多个字线，多个位线，多个普通存储器单元，访问控制电路，多个读出放大器，第一和第二复制位线，第一和第二复制 存储单元，以及第一和第二逻辑电路。 第一和第二复制存储器单元分别连接到第一和第二复制位线; 第一和第二逻辑电路的输入分别连接到第一和第二复制位线; 从第二逻辑电路的输出产生读出放大器使能信号; 并且该信号被提供给多个感测放大器。
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公开(公告)号：US20100177580A1
公开(公告)日：2010-07-15
申请号：US12687339
申请日：2010-01-14
CPC分类号： G11C11/413 , G11C7/08 , G11C7/22 , G11C7/227
摘要： Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.
摘要翻译： 即使使用复制位线的存储器的存储器容量更高，读出放大器使能信号的产生定时的波动也减小。 半导体集成电路器件包括多个字线，多个位线，多个普通存储器单元，访问控制电路，多个读出放大器，第一和第二复制位线，第一和第二复制 存储单元，以及第一和第二逻辑电路。 第一和第二复制存储器单元分别连接到第一和第二复制位线; 第一和第二逻辑电路的输入分别连接到第一和第二复制位线; 从第二逻辑电路的输出产生读出放大器使能信号; 并且该信号被提供给多个感测放大器。
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公开(公告)号：US20080143423A1
公开(公告)日：2008-06-19
申请号：US11943095
申请日：2007-11-20
IPC分类号： H03K3/01 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823878 , H01L21/823892 , H01L27/1203 , H03K19/0027 , H03K19/00315
摘要： The present invention is directed to realize high manufacture yield and compensate variations in threshold voltage of a MOS transistor with small overhead. A semiconductor integrated circuit includes a CMOS circuit for processing an input signal in an active mode, a control switch, and a control memory. The control switch supplies a pMOS body bias voltage and an nMOS body bias voltage to an N well in a pMOS transistor and a P well in an nMOS transistor, respectively, in the CMOS circuit. The control memory stores control information indicating whether or not the pMOS body bias voltage and the nMOS body bias voltage are supplied from the control switch to the N well in the pMOS transistor and the P well in the nMOS transistor, respectively, in the CMOS circuit in the active mode.
摘要翻译： 本发明旨在实现高制造成品率并补偿具有较小开销的MOS晶体管的阈值电压的变化。 半导体集成电路包括用于处理活动模式中的输入信号的CMOS电路，控制开关和控制存储器。 控制开关分别向CMOS电路中的nMOS晶体管中的pMOS晶体管和P阱中的N阱施加pMOS体偏置电压和nMOS体偏置电压。 控制存储器存储指示pMOS体偏置电压和nMOS体偏置电压是否从控制开关提供到CMOS电路中的nMOS晶体管中的pMOS晶体管和P阱中的N阱的控制信息 处于活动模式。
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公开(公告)号：US20080174359A1
公开(公告)日：2008-07-24
申请号：US11942939
申请日：2007-11-20
IPC分类号： H03K3/01
CPC分类号： H03K19/0008 , H03K2217/0018
摘要： A substrate bias technique is used in an active mode enabling a high yield, and an operating consumption power and the fluctuation of a signal delay in signal processing are reduced in the active mode. The additional PMOS and NMOS of the additional capacitance circuit are produced in the same production process as the PMOSs and the NMOSs of the CMOS circuits. The gate capacitance of the additional PMOS is coupled between the power supply wiring and the N well and the gate capacitance of the additional NMOS is coupled between the ground wiring and the P well. The noise on the power supply wiring is transmitted to the N well through the gate capacitance and the noise on the ground wiring is transmitted to the P well through the gate capacitance. The fluctuation of noise on the substrate bias voltage between the source and the well of PMOS and NMOS of the CMOS circuits is reduced.
摘要翻译： 在有源模式中使用基板偏压技术，能够实现高产量，并且在活动模式中降低了操作消耗功率和信号处理中的信号延迟的波动。 附加电容电路的附加PMOS和NMOS在与CMOS电路的PMOS和NMOS的生产过程相同的情况下生产。 附加PMOS的栅极电容耦合在电源布线和N阱之间，附加NMOS的栅极电容耦合在接地布线和P阱之间。 电源线上的噪声通过栅极电容传输到N阱，接地线上的噪声通过栅极电容传输到P阱。 CMOS电路的PMOS和NMOS的源极和阱之间的衬底偏置电压上的噪声波动减小。
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公开(公告)号：US08531872B2
公开(公告)日：2013-09-10
申请号：US13350340
申请日：2012-01-13
IPC分类号： G11C11/00
CPC分类号： G11C11/417
摘要： High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.
摘要翻译： 实现了高制造成品率，补偿了CMOS·SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据确定结果被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS·SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置电压施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。
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公开(公告)号：US08054871B2
公开(公告)日：2011-11-08
申请号：US12370338
申请日：2009-02-12
CPC分类号： H01L25/0657 , H01L24/16 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2924/14 , H01L2924/15311 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.
摘要翻译： 一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。 每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。 用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。
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公开(公告)号：US20090245445A1
公开(公告)日：2009-10-01
申请号：US12370338
申请日：2009-02-12
IPC分类号： H04L7/00
CPC分类号： H01L25/0657 , H01L24/16 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2924/14 , H01L2924/15311 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.
摘要翻译： 一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。 每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。 用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。
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公开(公告)号：US20100027322A1
公开(公告)日：2010-02-04
申请号：US12563231
申请日：2009-09-21
CPC分类号： G11C11/417
摘要： In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.
摘要翻译： 在本发明中，实现了高制造成品率，并补偿了CMOS.SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据测定结果分别被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS.SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。
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公开(公告)号：US20070297270A1
公开(公告)日：2007-12-27
申请号：US11812193
申请日：2007-06-15
申请人： Shigenobu Komatsu , Masanao Yamaoka
发明人： Shigenobu Komatsu , Masanao Yamaoka
CPC分类号： G11C8/08 , G11C8/18 , G11C11/412
摘要： The present invention provides a technique capable of achieving area reduction on a semiconductor integrated circuit device mounted with a time sharing virtual multi port memory or the like. By providing a configuration including a single port memory, data latch circuit for plural ports, a selector for selecting a port to be connected to the single port memory, a time sharing control signal generating circuit and the like, in which an operation termination signal inside the single port memory (a word line rising signal, a sense amplifier driving signal for data read or the like) is inputted to the time sharing control signal generating circuit to produce a port switching control signal and an operation control signal for the single port memory, a time sharing virtual multi port memory with a reduced area can be realized which requires no clock generating circuit for time sharing control newly.
摘要翻译： 本发明提供一种能够在安装有时间分配虚拟多端口存储器等的半导体集成电路装置上实现面积缩小的技术。 通过提供包括单端口存储器，用于多个端口的数据锁存电路，用于选择要连接到单端口存储器的端口的选择器，时间共享控制信号生成电路等，其中内部的操作终止信号 将单端口存储器（字线上升信号，用于数据读取的读出放大器驱动信号等）输入到时间共享控制信号发生电路，以产生用于单端口存储器的端口切换控制信号和操作控制信号 可以实现具有减小面积的虚拟多端口存储器的时间分配，这不需要新的时间分配控制的时钟发生电路。
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