公开(公告)号：US06326961B1

公开(公告)日：2001-12-04

申请号：US09164424

申请日：1998-09-30

申请人： Shih-Yin Lin ,  Chao-Ching Hwang ,  Ming-Yen Lin

发明人： Shih-Yin Lin ,  Chao-Ching Hwang ,  Ming-Yen Lin

IPC分类号： G09G500

CPC分类号： G09G5/008

摘要： This invention relates to an automatic detection method and apparatus for tuning the frequency and phase of displaying clock of a display to match the frequency and phase of pixel clock of a PC's display interface card. Based on the synchronized displaying clock, the image shown by digital display will be stable and bright in color. The automatic detection apparatus of invention includes a clock generation unit, a sampling unit, a data processing unit, an accumulation unit, and a decision unit. The clock generation unit creates a plurality of sampling clocks and according to these sampling packet sequences, the sampling unit samples and holds the pixel signals of image frames based on the pixel clock of display interface card, and then stores these data in its registers. The data processing unit calculates and transmits the differences of sampled data based on every sampling clock to accumulation unit that accumulates these differences, and transmits the sums of these differences to decision unit that finds out the sampling clock with the smallest transmitted sum, and let the phase and frequency of sampling clock with the smallest summed value as those of displaying clock of the PC display.

摘要翻译： 本发明涉及一种自动检测方法和装置，用于调整显示器的显示时钟的频率和相位以与PC显示接口卡的像素时钟的频率和相位相匹配。 基于同步显示时钟，数字显示所显示的图像颜色稳定亮丽。 本发明的自动检测装置包括时钟生成单元，采样单元，数据处理单元，累积单元和判定单元。 时钟生成单元创建多个采样时钟，并且根据这些采样分组序列，采样单元基于显示接口卡的像素时钟采样并保持图像帧的像素信号，然后将这些数据存储在其寄存器中。 数据处理单元基于每个采样时钟计算并发送采样数据的差异到积累这些差异的累加单元，并将这些差值的和发送到发现具有最小发送总和的采样时钟的判定单元，并且将 采样时钟的相位和频率最小，与显示PC显示时钟相同。

公开(公告)号：US08539277B2

公开(公告)日：2013-09-17

申请号：US13103991

申请日：2011-05-09

申请人： Yung-Chang Chang ,  Shih-Yin Lin ,  Chung-Kai Liu

发明人： Yung-Chang Chang ,  Shih-Yin Lin ,  Chung-Kai Liu

IPC分类号： G06F11/00

CPC分类号： H04L49/109 ,  H04L49/557

摘要： A manycore networks-on-chip (NoC) formed by a plurality of clusters is provided. The manycore NoC includes redundant routers and connection channels therefore is fault-tolerant as long as the numbers of damaged routers and damaged connection channels are under predetermined thresholds. Moreover, the NoC can retain its original logical topology without isolating any core after resetting the connection channels in response to the damaged routers and connection channels.

摘要翻译： 提供了由多个集群形成的行星网络（NoC）。 manycore NoC包括冗余路由器，因此只要损坏的路由器和损坏的连接信道的数量都处于预定阈值，则容错。 此外，NoC可以在重置连接通道以响应损坏的路由器和连接通道之后，保留原有的逻辑拓扑，而不隔离任何内核。

公开(公告)号：US20120155482A1

公开(公告)日：2012-06-21

申请号：US13103991

申请日：2011-05-09

申请人： Yung-Chang Chang ,  Shih-Yin Lin ,  Chung-Kai Liu

发明人： Yung-Chang Chang ,  Shih-Yin Lin ,  Chung-Kai Liu

IPC分类号： H04L12/56

CPC分类号： H04L49/109 ,  H04L49/557

摘要： A manycore networks-on-chip (NoC) formed by a plurality of clusters is provided. The manycore NoC includes redundant routers and connection channels therefore is fault-tolerant as long as the numbers of damaged routers and damaged connection channels are under predetermined thresholds. Moreover, the NoC can retain its original logical topology without isolating any core after resetting the connection channels in response to the damaged routers and connection channels.

摘要翻译： 提供了由多个集群形成的行星网络（NoC）。 manycore NoC包括冗余路由器，因此只要损坏的路由器和损坏的连接信道的数量都处于预定阈值，则容错。 此外，NoC可以在重置连接通道以响应损坏的路由器和连接通道之后，保留原有的逻辑拓扑，而不隔离任何内核。

公开(公告)号：US5844825A

公开(公告)日：1998-12-01

申请号：US707222

申请日：1996-09-03

申请人： Song-Tine Wang ,  Shih-Yin Lin ,  Shing-Wu Tung

发明人： Song-Tine Wang ,  Shih-Yin Lin ,  Shing-Wu Tung

IPC分类号： G06F5/01 ,  G06F7/76 ,  G11C19/00 ,  G11C19/28

CPC分类号： G11C19/00 ,  G06F5/01 ,  G11C19/28 ,  G06F7/768

摘要： A bidirectional shifter circuit is disclosed for shifting an inputted data word a chosen number of bit positions in either a first or a second chosen direction. The bidirectional shifter circuit is provided with a first bit-reversing circuit which receives an inputted data word. In response to choosing a first shift direction, the first bit-reversing circuit outputs the data word with the bits in their original order. In response to choosing the second shift direction, the first bit-reversing circuit outputs the data word with the bits in reverse order. A single-direction shifter circuit is provided which receives the data word outputted by the first bit-reversing circuit and shifts the received data word the chosen number of bit positions in the first direction. A second bit-reversing circuit is provided which receives the shifted data word and which, in response to choosing the first shift direction, outputs the data word with the bits in the same order as received and, in response to choosing the second shift direction, outputs the data word with the bits in reverse order.

摘要翻译： 公开了一种双向移位器电路，用于将输入的数据字在选择的第一或第二选择方向上移位所选择的位数位置。 双向移位器电路设置有接收输入数据字的第一位反转电路。 响应于选择第一移位方向，第一位反转电路以其原始顺序输出具有位的数据字。 响应于选择第二移位方向，第一位反转电路以相反的顺序输出具有位的数据字。 提供单向移位器电路，其接收由第一位反转电路输出的数据字，并将接收到的数据字在第一方向上移位所选择的位数位置。 提供了第二位反转电路，其接收移位的数据字，并且响应于选择第一移位方向，以与接收的相同次序输出数据字，并且响应于选择第二移位方向， 以相反的顺序输出数据字。

公开(公告)号：US5764971A

公开(公告)日：1998-06-09

申请号：US763670

申请日：1996-12-11

申请人： Shi-Sheng Shang ,  Shih-Yin Lin ,  Ching-Tang Chang ,  Bing-Huang Huang

发明人： Shi-Sheng Shang ,  Shih-Yin Lin ,  Ching-Tang Chang ,  Bing-Huang Huang

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/30152 ,  G06F9/30174 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861

摘要： An apparatus for producing in a superscalar pipelined system out-of-order execution and in-order completion of a set of macroinstructions, wherein the set of macroinstructions are translated into a set of microinstructions and the microinstructions are executed by the pipelined system and wherein at least some of said macroinstructions translate into more than one microinstruction, the apparatus including a result completion register having a plurality of entry fields each of which is used to indicate a completion state of a different corresponding microinstruction among the set of microinstructions; an interrupt condition register having a plurality of entry fields each of which is used to specify an occurrence of an interrupt condition during fetching, decoding, and executing a corresponding microinstruction among the set of microinstructions; an instruction size register having a plurality of entry fields which are used to identify locations of boundaries between macroinstructions among the set of microinstructions; a priority encoder which receives input from the result completion register and the instruction size register and which during operation generates an output indicating when all of the microinstructions of a next-in-line macroinstruction have been executed; and a retirement controller which receives the output from the priority encoder and which during operation in response to the output of the priority encoder retires the next-in-line macroinstruction when said output indicates that all of the microinstructions of the next-in-line macroinstruction have been executed.

摘要翻译： 一种用于以超标量流水线系统生产的装置，其无序执行和一系列宏指令的顺序完成，其中所述一组宏指令被转换成一组微指令，并且微指令由流水线系统执行，并且其中在 所述至少一些所述宏指令转换成多于一个微指令，所述装置包括具有多个输入字段的结果完成寄存器，每个输入字段用于指示所述一组微指令中的不同对应微指令的完成状态; 中断条件寄存器，具有多个输入字段，每个输入字段用于指定在所述一组微指令之间的取样，解码和执行相应的微指令期间出现中断条件; 指令大小寄存器，其具有多个输入字段，所述输入字段用于识别所述一组微指令之间的宏指令之间的边界的位置; 接收来自结果完成寄存器和指令大小寄存器的输入的优先编码器，并且在操作期间产生指示何时已经执行了下一行宏指令的所有微指令的输出; 以及退出控制器，其接收优先编码器的输出，并且在响应于优先级编码器的输出的操作期间退出控制器，当所述输出指示下一行大宏指令的所有微指令时，退出下一行宏指令 已经执行