摘要:
An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a clamp unit and a control circuit. The clamp unit provides a discharging path from a first power line to a first ground line. The control circuit receives a first power voltage from the first power line and a second power voltage from a second power line. Wherein, when the first power voltage and the second power voltage are applied, the control circuit generates an isolation signal to disconnect the discharging path. When the first power voltage and the second power voltage are not applied, the control circuit generates a trigger signal according to an electrostatic signal from the first power line to turn on the discharging path.
摘要:
An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a clamp unit and a control circuit. The clamp unit provides a discharging path from a first power line to a first ground line. The control circuit receives a first power voltage from the first power line and a second power voltage from a second power line. Wherein, when the first power voltage and the second power voltage are applied, the control circuit generates an isolation signal to disconnect the discharging path. When the first power voltage and the second power voltage are not applied, the control circuit generates a trigger signal according to an electrostatic signal from the first power line to turn on the discharging path.
摘要:
A semiconductor device, an electrostatic discharge protection device and manufacturing method thereof are provided. The electrostatic discharge protection device includes a gate, a gate dielectric layer, an N-type source region, an N-type drain region, an N-type doped region and a P-type doped region. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The N-type source region and the N-type drain region are disposed in the substrate at two sides of the gate, respectively. The N-type doped region is disposed in the N-type drain region and connects to the top of the N-type drain region. The P-type doped region is disposed under the N-type drain region and connects to the bottom of the N-type drain region.
摘要:
An electrostatic discharge (ESD) protection device including a modified lateral silicon-controlled rectifier (MLSCR) and a voltage control circuit is provided. The MLSCR has a first terminal, a second terminal and a control terminal connected to a first P+-type doped region, where the first terminal and the second terminal are electrically connected to a first line and a second line, respectively. The voltage control circuit is electrically connected to the first line, the second line and the control terminal. When an electrostatic pulse is appeared on the first line, the voltage control circuit provides a current path from the first line to the control terminal. When an input signal is supplied to the first line, the voltage control circuit receives a power voltage, and stops providing the current path according to the power voltage.
摘要:
An electrostatic discharge (ESD) protection device including a modified lateral silicon-controlled rectifier (MLSCR) and a voltage control circuit is provided. The MLSCR has a first terminal, a second terminal and a control terminal connected to a first P+-type doped region, where the first terminal and the second terminal are electrically connected to a first line and a second line, respectively. The voltage control circuit is electrically connected to the first line, the second line and the control terminal. When an electrostatic pulse is appeared on the first line, the voltage control circuit provides a current path from the first line to the control terminal. When an input signal is supplied to the first line, the voltage control circuit receives a power voltage, and stops providing the current path according to the power voltage.
摘要:
An ESD protection device including second P-type wells, first P+-type doped regions, first N+-type doped regions and a P-type substrate having a first P-type well, an N-type well and an N-type deep well is provided. The second P-type wells are disposed in the N-type deep well. The first P+-type doped regions and the first N+-type doped regions are respectively disposed in the first P-type well, the N-type well and the second P-type wells in alternation. The first P+-type doped region in the N-type well and the N-type deep well are electrically connected to the first connection terminal. The doped regions in the first P-type well and the P-type substrate are electrically connected to the second connection terminal. The second P-type wells and the first N+-type doped regions therein form a diode string connected in series between the first N+-type doped region of the N-type well and the second connection terminal.
摘要:
An ESD protection device including second P-type wells, first P+-type doped regions, first N+-type doped regions and a P-type substrate having a first P-type well, an N-type well and an N-type deep well is provided. The second P-type wells are disposed in the N-type deep well. The first P+-type doped regions and the first N+-type doped regions are respectively disposed in the first P-type well, the N-type well and the second P-type wells in alternation. The first P+-type doped region in the N-type well and the N-type deep well are electrically connected to the first connection terminal. The doped regions in the first P-type well and the P-type substrate are electrically connected to the second connection terminal. The second P-type wells and the first N+-type doped regions therein form a diode string connected in series between the first N+-type doped region of the N-type well and the second connection terminal.
摘要:
An electrostatic discharge protection device electrically connected between a pad and an internal circuit is provided and includes a capacitor, a first resistor, a voltage-drop element and an NMOS transistor. A first end of the capacitor is electrically connected to the pad. A first end of the first resistor is electrically connected to a second end of the capacitor, and a second end of the first resistor is electrically connected to ground. The NMOS transistor and the voltage-drop element are connected in series between the pad and the ground, a gate of the NMOS transistor is electrically connected to the second end of the capacitor, and a bulk of the NMOS transistor is electrically connected to the ground.