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    Word Line Decoder Circuit Apparatus and Method
    1.
    发明申请
    Word Line Decoder Circuit Apparatus and Method 有权
    字线解码器电路设备及方法

    公开(公告)号：US20110069571A1

    公开(公告)日：2011-03-24

    申请号：US12816960

    申请日：2010-06-16

    申请人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    发明人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC分类号： G11C7/00 ,  G11C8/10

    CPC分类号： G11C16/16

    摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.

    摘要翻译： 该技术的一个实施例是一种装置，存储器集成电路。 存储器集成电路具有字线地址解码电路。 该电路允许选择单个字线以具有擦除电压。 解码器电路包括反相器和逻辑。 逆变器具有输入和控制字线的输出以执行擦除操作。 输入的电压范围在第一参考电压和第二电压基准之间延伸。 电压基准的示例是电压源和地。 在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。 解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

    Word line decoder circuit apparatus and method
    2.
    发明授权
    Word line decoder circuit apparatus and method 有权
    字线解码电路装置及方法

    公开(公告)号：US08638636B2

    公开(公告)日：2014-01-28

    申请号：US12816960

    申请日：2010-06-16

    申请人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    发明人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC分类号： G11C8/00

    CPC分类号： G11C16/16

    摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.

    摘要翻译： 该技术的一个实施例是一种装置，存储器集成电路。 存储器集成电路具有字线地址解码电路。 该电路允许选择单个字线以具有擦除电压。 解码器电路包括反相器和逻辑。 逆变器具有输入和控制字线的输出以执行擦除操作。 输入的电压范围在第一参考电压和第二电压基准之间延伸。 电压基准的示例是电压源和地。 在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。 解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

    Method and Apparatus for the Erase Suspend Operation
    4.
    发明申请
    Method and Apparatus for the Erase Suspend Operation 有权
    擦除挂起操作的方法和装置

    公开(公告)号：US20120057410A1

    公开(公告)日：2012-03-08

    申请号：US12875003

    申请日：2010-09-02

    申请人： Chuan-Ying Yu ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Kuen-Long Chang

    发明人： Chuan-Ying Yu ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Kuen-Long Chang

    IPC分类号： G11C16/16

    CPC分类号： G11C16/16 ,  G11C16/345 ,  G11C16/3454

    摘要： Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.

    摘要翻译： 非易失性存储器的各个方面具有改进的擦除暂停过程。 偏移布置被施加到经历由擦除暂停过程中断的擦除过程的擦除扇区的字线。 结果，由于擦除扇区的任何被擦除的非易失性存储单元的漏电流减少，因此在诸如读操作或程序操作的擦除暂停期间执行的另一操作具有更精确的结果。

    Apparatus of Supplying Power and Method Therefor
    6.
    发明申请
    Apparatus of Supplying Power and Method Therefor 有权
    供电装置及其方法

    公开(公告)号：US20110227552A1

    公开(公告)日：2011-09-22

    申请号：US12820422

    申请日：2010-06-22

    申请人： Chih-Ting Hu ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Wu-Chin Peng ,  Kuen-Long Chang ,  Ken-Hui Chen

    发明人： Chih-Ting Hu ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Wu-Chin Peng ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC分类号： G05F3/02

    CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M2001/0032 ,  Y02B70/16

    摘要： A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing.

    摘要翻译： 提供电源装置和供电方法。 用于具有第一功率信号的系统中的装置包括辅助单元和电源装置。 辅助单元选择性地输出根据第一功率信号的至少一个维持信号。 电源装置输出第二电力信号，其中电源装置根据至少一个维持信号维持第二电力信号，例如处于非空闲状态，例如空闲或待机状态或其他合适的定时。

    Method and apparatus for reducing erase disturb of memory by using recovery bias
    7.
    发明授权
    Method and apparatus for reducing erase disturb of memory by using recovery bias 有权
    通过使用恢复偏压来减少存储器的擦除干扰的方法和装置

    公开(公告)号：US08982640B2

    公开(公告)日：2015-03-17

    申请号：US13426985

    申请日：2012-03-22

    申请人： Chun Hsiung Hung ,  Bo-Chang Wu ,  Kuen-Long Chang ,  Ken-Hui Chen

    发明人： Chun Hsiung Hung ,  Bo-Chang Wu ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3431 ,  G11C16/14 ,  G11C16/3418 ,  G11C16/344

    摘要： A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.

    摘要翻译： 非易失性存储器阵列被分成多个存储器组。 非易失性存储器阵列接收擦除命令以擦除第一组存储器组，而不是第二组存储器组。 控制电路响应于擦除命令来擦除第一组存储器组，通过应用恢复偏压布置来调整第二组存储器组的至少一个存储器组中的存储器单元的阈值电压。 通过将恢复偏压装置应用于第二组存储器组的至少一个存储器组中的存储器单元，至少部分地在恢复偏压装置期间校正擦除干扰。

    Semiconductor device including memory cells and current limiter
    8.
    发明授权
    Semiconductor device including memory cells and current limiter 有权
    半导体器件包括存储单元和限流器

    公开(公告)号：US07355903B2

    公开(公告)日：2008-04-08

    申请号：US11181983

    申请日：2005-07-15

    申请人： Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Kuen-Long Chang

    发明人： Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Kuen-Long Chang

    IPC分类号： G11C7/10

    CPC分类号： G11C16/24

    摘要： A semiconductor device, including a memory cell having a control gate, a source and drain; and a current limiting circuit coupled to the source. The current limiting circuit may be configured to limit a current between the drain and source to not exceed a predetermined value; the current being generated in response to application of first and second voltages to the control gate and drain, respectively. The current limiting circuit may include a transistor comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal may include a source of the transistor, the third terminal may include a drain of the transistor, and the second terminal may include a gate of the transistor, and wherein a stable bias may be applied to the second terminal of the transistor.

    摘要翻译： 一种半导体器件，包括具有控制栅极，源极和漏极的存储单元; 以及耦合到源极的限流电路。 电流限制电路可以被配置为将漏极和源极之间的电流限制为不超过预定值; 响应于分别向控制栅极和漏极施加第一和第二电压而产生电流。 电流限制电路可以包括包括第一端子，第二端子和第三端子的晶体管，其中第一端子可以包括晶体管的源极，第三端子可以包括晶体管的漏极，并且第二端子可以 包括晶体管的栅极，并且其中可以将稳定的偏压施加到晶体管的第二端子。

    Memory chip and method for operating the same
    9.
    发明授权
    Memory chip and method for operating the same 有权
    内存芯片及其操作方法

    公开(公告)号：US08203896B2

    公开(公告)日：2012-06-19

    申请号：US12911173

    申请日：2010-10-25

    申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

    发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

    IPC分类号： G11C7/00 ,  G11C11/50 ,  G11C7/04

    CPC分类号： G11C29/022 ,  G11C29/02

    摘要： A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

    摘要翻译： 提供了一种存储芯片及其操作方法。 存储器芯片包括多个焊盘。 该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。

    Memory chip and method for operating the same
    10.
    发明授权
    Memory chip and method for operating the same 有权
    内存芯片及其操作方法

    公开(公告)号：US07885129B2

    公开(公告)日：2011-02-08

    申请号：US12256042

    申请日：2008-10-22

    申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

    发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

    IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C11/50

    CPC分类号： G11C29/022 ,  G11C29/02

    摘要： A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

    摘要翻译： 提供了一种存储芯片及其操作方法。 存储器芯片包括多个焊盘。 该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。