公开(公告)号：US5341038A

公开(公告)日：1994-08-23

申请号：US825977

申请日：1992-01-27

Applicant: William E. Headen, Jr.

Inventor： William E. Headen, Jr.

IPC: H03K5/24 ,  H03K17/30 ,  H03K3/33

CPC classification number: H03K17/30 ,  H03K5/2409

Abstract: An error detection circuit having an output transistor of one conductivity type and a sense transistor and error detector transistor of an opposite conductivity type. An input voltage is provided at the collector of the output transistor and an output voltage is taken from the emitter of the output transistor. An emitter of the sense transistor is connected to the input voltage and the collector of the sense transistor is connected to the base of the output transistor. An emitter of the error detector transistor is connected to the collector of the sense transistor and a base of the error detector transistor is connected to the base of the sense transistor. The error detector transistor conducts when the sense transistor saturates indicating that the input voltage and output voltage have come within a predetermined voltage of one another.

Abstract translation: 具有一种导电类型的输出晶体管和一种相反导电类型的检测晶体管和误差检测器晶体管的误差检测电路。 在输出晶体管的集电极处提供输入电压，并且从输出晶体管的发射极获取输出电压。 感测晶体管的发射极连接到输入电压，并且感测晶体管的集电极连接到输出晶体管的基极。 误差检测器晶体管的发射极连接到感测晶体管的集电极，并且误差检测器晶体管的基极连接到感测晶体管的基极。 当感测晶体管饱和时，误差检测器晶体管导通，表示输入电压和输出电压已经达到彼此的预定电压。

公开(公告)号：US4794281A

公开(公告)日：1988-12-27

申请号：US822083

申请日：1986-01-24

Applicant: Keith K. Onodera ,  Alex B. Djenguerian

Inventor： Keith K. Onodera ,  Alex B. Djenguerian

IPC: H03K19/00 ,  H03K19/013 ,  H03K19/088 ,  H03K3/33 ,  H03K5/13 ,  H03K17/16

CPC classification number: H03K19/001 ,  H03K19/0136

Abstract: A totem-pole transistor circuit in the output stage of a logic device includes, in the base circuit of the current sink transistor, a discharge transistor responsive to each transition of a circuit input signal for discharging the parasitic base capacitance of the sink transistor, and a circuit for delaying the delivery of the input signal to the discharge transistor. The delay results in postponing the transition of the discharge transistor from one operational state to another. This causes the transitions of the discharge transistor to lag the transitions of the totem-pole pair which occur simultaneously with input signal changes. Thus, the discharge transistor is held on for a period of time sufficient to discharge the parasitic capacitance when the current-sink transistor turns off. This speeds up the turn-off of the sink transistor. After the period elapses, the discharge transistor turns off. Then, when base current is supplied to the current-sink transistor to turn it on, the discharge transistor is held off for an amount of time during which all of the base current is provided to the current-sink transistor, causing it to be quickly switched on. Then the discharge transistor is turned on, permitting it to discharge the parasitic capacitance of the current-sink transistor at the next input signal transition.

Abstract translation: 在逻辑器件的输出级中的图腾柱晶体管电路包括在电流吸收晶体管的基极电路中，对放电晶体管的寄生基极电容进行放电的电路输入信号的每个转变进行响应的放电晶体管，以及 用于延迟将输入信号传送到放电晶体管的电路。 延迟导致放电晶体管从一个操作状态转变到另一个操作状态。 这导致放电晶体管的转变滞后于与输入信号变化同时发生的图腾柱对的转变。 因此，放电晶体管保持导通一段时间，足以在导通晶体管截止时对寄生电容进行放电。 这将加速接收晶体管的关断。 经过一段时间后，放电晶体管截止。 然后，当将基极电流提供给电流沉降晶体管以使其导通时，放电晶体管被截止一段时间，在该时间期间，所有基极电流被提供给电流沉降晶体管，使得其快速 切换到。 然后放电晶体管导通，允许放电晶体管在下一个输入信号转变时放电电流吸收晶体管的寄生电容。

公开(公告)号：US4769560A

公开(公告)日：1988-09-06

申请号：US13793

申请日：1987-02-12

Applicant: Keizo Tani ,  Junichi Nakao ,  Eiji Kotani

Inventor： Keizo Tani ,  Junichi Nakao ,  Eiji Kotani

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/732 ,  H03F1/32 ,  H03F3/343 ,  H03K3/33 ,  H01L27/02 ,  H03K17/56

CPC classification number: H03F1/32 ,  H03F3/3435

Abstract: An additional p-n junction diode, having a forward bias voltage smaller than a forward bias voltage between the base and emitter of a first-stage specific transistor of 3-stage Darlington connected npn transistors, is electrically connected in parallel between a p-type base layer and an n-type collector layer of the specific transistor. The polarities of the p-type and n-type layers of the diode are respectively the same as those of the parallel-connected p-type base and n-type collector layers of the specific transistor.

Abstract translation: 具有小于三阶段达林顿连接的npn晶体管的第一级特定晶体管的基极和发射极之间的正向偏置电压的正向偏置电压的附加pn结二极管并联电连接在p型基极层 和特定晶体管的n型集电极层。 二极管的p型和n型层的极性分别与特定晶体管的并联p型基极和n型集电极层的极性相同。

公开(公告)号：US4751403A

公开(公告)日：1988-06-14

申请号：US743079

申请日：1985-06-10

Applicant: Hitoshi Maekawa ,  Michitaka Ohsawa ,  Kunio Ando

Inventor： Hitoshi Maekawa ,  Michitaka Ohsawa ,  Kunio Ando

IPC: H03K17/042 ,  H03K17/60 ,  G05F1/40 ,  H03K3/33

CPC classification number: H03K17/601 ,  H03K17/04213

Abstract: A driving circuit uses an output transistor and a driving transformer with a secondary coil being connected to the base of the output transistor. In order to get a high speed switching circuit without thermal runaway, the storage period of the output transistor is detected. A signal supplied to a primary coil of the driving transformer, for example, a driving pulse, is controlled in response to the detected value of the storage period. By minimizing the value of the storage period, it becomes possible to minimize a fall time of the output transistor, so that a stability of the driving circuit can be maintained.

Abstract translation: 驱动电路使用输出晶体管和驱动变压器，其中次级线圈连接到输出晶体管的基极。 为了获得没有热失控的高速开关电路，检测输出晶体管的存储周期。 响应于检测到的存储期间的值，控制提供给驱动变压器的初级线圈的信号，例如驱动脉冲。 通过使存储周期的值最小化，可以使输出晶体管的下降时间最小化，从而可以保持驱动电路的稳定性。

公开(公告)号：US4749876A

公开(公告)日：1988-06-07

申请号：US944981

申请日：1986-12-22

Applicant: Allan R. Gale ,  David J. Gritter

Inventor： Allan R. Gale ,  David J. Gritter

IPC: H03K17/0414 ,  H03K17/0422 ,  H03K17/082 ,  H03K3/26 ,  G05F1/40 ,  H03K3/33

CPC classification number: H03K17/0826 ,  H03K17/0414 ,  H03K17/0422

Abstract: A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Abstract translation: 一种用于功率晶体管的饱和状态调节器系统，其实现了贝克钳位的调节目标，但不将过多的基极驱动电流转储到晶体管输出电路中。 通过有源反馈电路感测并使用晶体管的基极驱动电流，以产生通过线性工作FET调制基极驱动电流的误差信号。 独立监控功率晶体管的集电极基极电压，以产生第二个误差信号，该误差信号也用于调节基极驱动电流。 电流敏感电路作为限幅器工作。 此外，公开了一种故障安全定时电路，其在晶体管在输入信号转换之后的预定时间内不会导通的情况下自动复位到断开状态。

公开(公告)号：US4740719A

公开(公告)日：1988-04-26

申请号：US928001

申请日：1986-11-07

Applicant: Youichirou Taki

Inventor： Youichirou Taki

IPC: H03K19/088 ,  H03K19/013 ,  H03K19/20 ,  H03K3/01 ,  H03K3/33 ,  H03K17/16

CPC classification number: H03K19/0136

Abstract: A semiconductor integrated circuit device including: a first transistor whose base receives an input signal, and whose collector is connected to a high power supply voltage; a second transistor whose base is conducted to the emitter of said first transistor and whose emitter is connected to a low power supply voltage; a third transistor whose base is connected to the collector of said first transistor, whose collector is connected to said high power supply voltage, and whose emitter is connected to the collector of said second transistor directly or via a load element; and a fourth transistor whose base is connected to the emitter of said third transistor, whose emitter is connected to said low power supply voltage, and from whose collector an output signal of said semiconductor integrated circuit device is taken out.

Abstract translation: 一种半导体集成电路器件，包括：第一晶体管，其基极接收输入信号，其集电极连接到高电源电压; 第二晶体管，其基极被传导到所述第一晶体管的发射极并且其发射极连接到低电源电压; 第三晶体管，其基极连接到所述第一晶体管的集电极，其集电极连接到所述高电源电压，并且其发射极直接或经由负载元件连接到所述第二晶体管的集电极; 以及第四晶体管，其基极连接到所述第三晶体管的发射极，其发射极连接到所述低电源电压，并且从其集电极连接所述半导体集成电路器件的输出信号。

公开(公告)号：US4736380A

公开(公告)日：1988-04-05

申请号：US858405

申请日：1986-04-30

Applicant: Agoston Agoston

Inventor： Agoston Agoston

IPC: H01S5/06 ,  H01S5/042 ,  H03K3/286 ,  H03K3/33 ,  H03K17/60 ,  H01S3/096

CPC classification number: H03K3/33 ,  H01S5/042 ,  H03K17/601 ,  H03K3/286

Abstract: A reverse current transmitted through an initially forward biased step-recovery diode causes the step-recovery diode to switch from the forward biased state to a reverse biased state, thereby developing an abruptly rising reverse bias voltage across the step-recovery diode. The abruptly rising reverse bias voltage is applied across a series combination of a capacitor and a laser diode, connected in parallel with the step-recovery diode to force a short, abrupt forward current pulse through the laser diode, thereby causing the laser diode to emit a short optical pulse.

Abstract translation: 通过初始正向偏置的阶跃恢复二极管传输的反向电流使得步进恢复二极管从正向偏置状态切换到反向偏置状态，从而在逐步恢复二极管两端产生突然上升的反向偏置电压。 突然上升的反向偏置电压施加在电容器和激光二极管的串联组合上，与步进恢复二极管并联连接，以迫使通过激光二极管的短暂的，突然的正向电流脉冲，从而使激光二极管发射 一个短的光脉冲。

公开(公告)号：US4728817A

公开(公告)日：1988-03-01

申请号：US12774

申请日：1987-02-09

Applicant: Ralph D. Jessee ,  Joseph M. Urish

Inventor： Ralph D. Jessee ,  Joseph M. Urish

IPC: H02M7/537 ,  H03K17/0412 ,  H03K17/60 ,  H03K17/615 ,  H03K17/66 ,  G05F1/56 ,  H03K3/33

CPC classification number: H03K17/04126 ,  H03K17/601 ,  H03K17/615 ,  H03K17/666

Abstract: A transistor drive circuit includes a driver transistor and a power switching transistor connected in a Darlington configuration which receives turn-on and turn-off signals from a drive transformer. A capacitor is provided for connection between the driver transistor base and the switching transistor emitter during a turn-off period such that the voltage on the capacitor hastens turn-off of the driver transistor and the switching transistor. A diode connected between the emitter and the base of the driver transistor provides for continuing current flow from the capacitor following turn-off of the driver transistor but prior to turn-off of the switching transistor. After the switching transistor has turned off, the capacitor is recharged prior to the presence of a turn-on signal from the drive transformer.

公开(公告)号：US4719373A

公开(公告)日：1988-01-12

申请号：US45216

申请日：1987-04-30

Applicant: Ikuro Masuda ,  Kazuo Kato ,  Takao Sasayama ,  Yoji Nishio ,  Shigeo Kuboki ,  Masahiro Iwamura

Inventor： Ikuro Masuda ,  Kazuo Kato ,  Takao Sasayama ,  Yoji Nishio ,  Shigeo Kuboki ,  Masahiro Iwamura

IPC: H03K19/08 ,  H01L27/06 ,  H03K19/01 ,  H03K19/017 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/0952 ,  H03K17/60 ,  H03K3/33

CPC classification number: H01L27/0623 ,  H03K19/01 ,  H03K19/01721 ,  H03K19/09448

Abstract: A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

公开(公告)号：US4675547A

公开(公告)日：1987-06-23

申请号：US717162

申请日：1985-03-28

Applicant: Rolf Eichenwald

Inventor： Rolf Eichenwald

IPC: H03K17/0412 ,  H03K17/16 ,  H03K17/795 ,  H03K3/26 ,  H03K3/33 ,  H03K3/42

CPC classification number: H03K17/04126 ,  H03K17/16 ,  H03K17/795

Abstract: In a base drive circuit for a high power transistor, an external signal is applied to the circuit by an optical coupler. In response to the external signal, the circuit provides a positive current to the high power transistor in order turn it on. The positive constant current is characterized by an initial spike that prevents any localized hot spots from developing in the high power transistor and thereafter the positive current becomes constant. The circuit also provides a constant negative current when the external signal is removed, thereby quickly turning off the high power transistor. The optical coupler and a time delay device provide the circuit with high noise immunity.

Abstract translation: 在用于大功率晶体管的基极驱动电路中，外部信号由光耦合器施加到电路。 响应于外部信号，电路向高功率晶体管提供正电流，以便将其导通。 正恒定电流的特征在于初始尖峰，其防止在高功率晶体管中发生任何局部热点，此后正电流变得恒定。 当外部信号被去除时，电路还提供恒定的负电流，从而快速关断大功率晶体管。 光耦合器和时间延迟器件为电路提供了高抗噪声能力。