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    FALL DETECTOR AND ALERT SYSTEM
    1.
    发明申请
    FALL DETECTOR AND ALERT SYSTEM 审中-公开
    落地检测器和报警系统

    公开(公告)号：US20160260311A1

    公开(公告)日：2016-09-08

    申请号：US15063037

    申请日：2016-03-07

    Applicant: Shintaro Asano

    Inventor： Shintaro Asano

    IPC: G08B21/04 ,  A43B3/00

    CPC classification number: G08B21/0446 ,  A43B3/0005 ,  A43B3/0015 ,  A43B17/00 ,  A61B5/0022 ,  A61B5/1038 ,  A61B5/1117 ,  A61B5/112 ,  A61B5/6807 ,  A61B2562/0247 ,  A62B33/00 ,  G06F19/00 ,  G08B25/014 ,  G08B25/08 ,  G16H40/67

    Abstract: A fall detection and alert system and associated methods are described. The system includes a right footwear item and a left footwear item, each of which includes foot pressure sensors, communications circuitry configured to transmit foot pressure signals from the pressure sensors to a mobile device, such as a smartphone, and a power source. The system also includes an application for the mobile device that causes the mobile device to receive transmitted foot pressure signals from the communications circuitry of the footwear, analyze the foot pressure signals to determine whether a wearer of the footwear items has fallen, display a warning if it is determined that the wearer of the footwear items has fallen, along with an option to cancel the warning, and send a signal to a caregiver if the warning has not been canceled within a predetermined period of time.

    Abstract translation: 描述了跌倒检测和警报系统及相关方法。 该系统包括右鞋类物品和左鞋类物品，每个物品包括足部压力传感器，配置成将压力信号从压力传感器传送到诸如智能电话的移动设备和电源的通信电路。 该系统还包括移动设备的应用，其使得移动设备从鞋的通信电路接收传送的脚压信号，分析脚压信号以确定鞋类物品的佩戴者是否已经下降，如果 确定鞋类物品的穿戴者已经下降，以及取消警告的选项，并且如果在预定时间段内尚未取消警告，则向照顾者发送信号。

    Semiconductor device and method of manufacturing same
    2.
    发明申请
    Semiconductor device and method of manufacturing same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20080211058A1

    公开(公告)日：2008-09-04

    申请号：US12007844

    申请日：2008-01-16

    Applicant: Shintaro Asano ,  Kazutoshi Fukahori ,  Shinichi Miyatake

    Inventor： Shintaro Asano ,  Kazutoshi Fukahori ,  Shinichi Miyatake

    IPC: H01L21/441 ,  H01L29/86

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device comprises one or more elements subjected to trimming, formed on a main surface side of a silicon substrate and that is/are to be laser trimmed, and an electrode lead of the element subjected to trimming disposed below the position of the element subjected to trimming. The electrode lead subjected to trimming comprises a diffusion layer formed in an uppermost layer of the silicon substrate. The diffusion layer is covered with a protection film made of doped polysilicon and is directly formed on the silicon substrate.

    Abstract translation: 半导体器件包括经过修整的一个或多个元件，形成在硅衬底的主表面侧并且被激光修整，并且经受修整的元件的电极引线设置在被施加的元件的位置下方 修剪 经过修整的电极引线包括形成在硅衬底的最上层中的扩散层。 扩散层被由掺杂多晶硅制成的保护膜覆盖并直接形成在硅衬底上。

    Method and system for remotely backing up a computer memory utilizing a global communications network
    3.
    发明授权
    Method and system for remotely backing up a computer memory utilizing a global communications network 失效
    使用全球通信网络远程备份计算机存储器的方法和系统

    公开(公告)号：US07203861B1

    公开(公告)日：2007-04-10

    申请号：US09802093

    申请日：2001-03-08

    Applicant: Shintaro Asano

    Inventor： Shintaro Asano

    IPC: G06F11/00

    CPC classification number: G06F11/1464

    Abstract: Embodiments of the present invention relate to a method and system for remotely backing-up computer memories utilizing a global communications network. An embodiment of the present invention utilizes the INTERNET to access a plurality of computers. The plurality of computers is in electrical communication with a central office. In one embodiment of the invention, a computer located in the central office administers a memory back-up procedure at a customer's location. The central office computer may also assess whether the memory back-up procedure has been successfully completed, and if not, send an electronic notification to a predetermined system or individual that a failure has occurred, and to automatically provide repairs.

    Abstract translation: 本发明的实施例涉及一种利用全球通信网络远程备份计算机存储器的方法和系统。 本发明的实施例利用INTERNET来访问多个计算机。 多个计算机与中心局电连通。 在本发明的一个实施例中，位于中央局的计算机在客户的位置管理存储器备份过程。 中央办公室计算机还可以评估存储器备份过程是否已经成功完成，如果不是，则向发生故障的预定系统或个人发送电子通知，并自动提供维修。

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US5892284A

    公开(公告)日：1999-04-06

    申请号：US63712

    申请日：1998-04-21

    Applicant: Shintaro Asano

    Inventor： Shintaro Asano

    IPC: H01L21/768 ,  H01L21/78 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L21/78 ,  H01L23/528 ,  H01L2924/0002

    Abstract: A semiconductor integrated circuit includes upper level and lower level substrate interconnection layers which are positioned in a scribing line area and which are separated from each other an interlayer insulating film formed therebetween. For planarization, an upper surface of the interlayer insulating film is coated with an SOG silicon oxide insulating film formed by coating an SOG organic solution by means of a spin coating. The lower level substrate interconnection layer is divided into a plurality of segments separated from each other by gaps which are provided at a plurality of different locations and which allow the SOG organic solution to escape through the gaps by a centrifugal force when the SOG organic solution is applied by the spin coating. The upper level substrate interconnection layer is electrically connected to the plurality of segments of the lower level substrate interconnection layers through contacts hole formed to penetrate through the interlayer insulating film.

    Abstract translation: 半导体集成电路包括位于划线区域中的上层和下层衬底互连层，并且彼此分离形成在其间的层间绝缘膜。 为了平坦化，层间绝缘膜的上表面涂覆有通过旋涂涂覆SOG有机溶液而形成的SOG氧化硅绝缘膜。 下层衬底互连层被分成多个段，这些间隔通过设置在多个不同位置处的间隙彼此分开，并且当SOG有机溶液为SOG有机溶液为SOG时，允许SOG有机溶液通过离心力从间隙逸出 通过旋涂施加。 上层衬底互连层通过形成为穿透层间绝缘膜的接触孔电连接到下层衬底互连层的多个段。

    System and method for processing product order placed through a network
    6.
    发明申请
    System and method for processing product order placed through a network 审中-公开
    通过网络处理产品订单的系统和方法

    公开(公告)号：US20060206390A1

    公开(公告)日：2006-09-14

    申请号：US11329359

    申请日：2006-01-10

    Applicant: Shintaro Asano

    Inventor： Shintaro Asano

    IPC: G06Q30/00

    CPC classification number: H04L67/306 ,  G06Q20/00 ,  G06Q20/12 ,  G06Q20/20 ,  G06Q20/32 ,  G06Q30/06 ,  G06Q30/0601 ,  G06Q50/12 ,  H04L69/329

    Abstract: The invention provides a communications system and method for receiving at a network computer system electronic information from a multiple of sites (consumers) on a communications network, such as the Internet, and formatting and transmitting the information from the network computer system over a telecommunications network using simple protocols to a selected site. The invention provides a communications system and method particularly suited for processing electronic consumer orders including receiving at a network computer system a multiple of electronic order messages placed by consumers through a communications network or the Internet and transmitting the order messages to a multiple of designated vendors that do not have network communication capabilities or Internet access. The communications system and method enable the designated vendors without access to the Internet to receive electronic orders from consumers.

    Abstract translation: 本发明提供一种通信系统和方法，用于在网络计算机系统处从诸如因特网之类的通信网络上的多个站点（消费者）接收电子信息，以及通过电信网络格式化和发送来自网络计算机系统的信息 使用简单的协议到选定的站点。 本发明提供了一种特别适合于处理电子消费者订单的通信系统和方法，包括在网络计算机系统处接收消费者通过通信网络或因特网放置的多个电子订单消息，并将订单消息发送到多个指定供应商， 没有网络通信功能或Internet访问。 通信系统和方法使指定的供应商无需访问互联网即可接收消费者的电子订单。

    Archive computer system and method for storage and retrieval of records
    8.
    发明授权
    Archive computer system and method for storage and retrieval of records 失效
    归档计算机系统和存储和检索记录的方法

    公开(公告)号：US06651076B1

    公开(公告)日：2003-11-18

    申请号：US09574592

    申请日：2000-05-19

    Applicant: Shintaro Asano

    Inventor： Shintaro Asano

    IPC: G06F1200

    CPC classification number: G06F17/30309 ,  G06F17/3056 ,  Y10S707/99943 ,  Y10S707/99953 ,  Y10S707/99955

    Abstract: A computer network system is set forth for bi-directionally communicating information in a predetermined format between a plurality of client computers and a server. The system includes an archive computer system having a mass storage database. The archive computer system can store and retrieve a number of client records to and from the mass storage database. Prior to storing each client record in the database, the record is appended with a transparent sector. The transparent sector includes software application and version related information which is associated with the software application and version used to generate the record. Upon retrieval of the record from the mass storage database, the contents of the transparent sector is compared to a table to insure the requesting client computer includes a software application and version compatible with the retrieved record.

    Abstract translation: 提出了一种计算机网络系统，用于在多个客户端计算机和服务器之间以预定格式双向传达信息。 该系统包括具有大容量存储数据库的归档计算机系统。 归档计算机系统可以存储和检索大量存储数据库中的大量客户端记录。 在将每个客户端记录存储在数据库中之前，该记录将附加一个透明扇区。 透明部门包括与用于生成记录的软件应用程序和版本相关联的软件应用程序和版本相关信息。 在从大容量存储数据库检索记录时，将透明扇区的内容与表进行比较，以确保请求客户端计算机包括与所检索的记录兼容的软件应用和版本。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US5267208A

    公开(公告)日：1993-11-30

    申请号：US656525

    申请日：1991-02-19

    Applicant: Shintaro Asano

    Inventor： Shintaro Asano

    IPC: H01L27/11 ,  G11C7/02

    CPC classification number: H01L27/1112

    Abstract: By provided a dummy region, having a shape similar to and being formed in the same process as, the active regions having transistors that constitute memory cells formed therein, between two transistors, the spacing between the active region and the dummy region is made to be equal to the spacing between other transistors. By reducing the nonuniformity in the gate width of the transistors within the memory cell array regions with the above arrangement, it is possible to prevent the reduction of the transistor performance, and to prevent a performance reduction and the generation of malfunctions due to a delay in the data output time of the semiconductor memory device.

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5239201A

    公开(公告)日：1993-08-24

    申请号：US982003

    申请日：1992-11-24

    Applicant: Shintaro Asano

    Inventor： Shintaro Asano

    IPC: H01L23/528 ,  H01L27/11

    CPC classification number: H01L27/1112 ,  H01L23/528 ,  H01L2924/0002

    Abstract: A semiconductor memory device is disclosed which has a multilevel conductor structure including conductors of a lower-level and conductors of an upper-level. The memory device comprises first and second memory cells disposed adjacent to and space from each other, a first conductor at the lower-level included in the first memory cell to constitute the first memory cell and having a portion formed along the space between the memory cells, a second conductor at the lower-level included in the second memory cell to constitute the second memory cell and having a portion formed along the space between the memory cells, a third conductor at the upper-level formed to pass along the space between the first and second memory cells, and a dummy conductor at the lower-level formed under the third conductor to lie between the portion of the first conductor and the portion of the second conductor.

    Abstract translation: 公开了一种半导体存储器件，其具有包括下层导体和上层导体的多层导体结构。 存储器件包括彼此相邻并且彼此间隔开的第一和第二存储器单元，包括在第一存储器单元中的下层的第一导体构成第一存储单元并具有沿着存储单元之间的空间形成的部分 位于第二存储单元中的包括在第二存储单元中的下层的第二导体构成第二存储单元，并且具有沿着存储单元之间的空间形成的部分，上层的第三导体形成为沿着第二存储单元之间的空间 第一和第二存储单元，以及形成在第三导体下面的下层的虚拟导体，以位于第一导体的部分和第二导体的部分之间。

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