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1.发明授权Electron multiplying device having multiple dynode stages encased by a housing 失效具有由壳体封装的多个倍增电极级的电子倍增装置
公开(公告)号：US5446275A
公开(公告)日：1995-08-29
申请号：US63418
申请日：1993-05-19
摘要： The electron multiplying device according to this invention comprises an electron multiplying unit including dynodes arranged in a plurality of stages. The electron multiplying unit has an incidence opening for an energy beam to be multiplied to enter through, and has the proximal end secured to a base. There is provided a casing for housing the electron multiplying unit. The forward edge of the casing is secured to the base, and a space defined by the base and the casing houses the electron multiplying unit. The casing has an entrance window formed at a position opposed to the incidence opening. Energy beams enter the electron multiplying unit through the entrance window, but the electron multiplying unit itself is housed in the casing to be protected from surrounding air flow and unnecessary energy beams not to be measured.
摘要翻译： 根据本发明的电子倍增装置包括电子倍增单元，其包括以多级布置的倍增电极。 电子倍增单元具有用于能量束的入射开口，该能量束被乘以通过，并且其近端固定到基部。 设置有用于容纳电子倍增单元的壳体。 壳体的前缘固定到基座，由基座和壳体限定的空间容纳电子倍增单元。 壳体具有形成在与入射开口相对的位置处的入口窗口。 能量束通过入口窗进入电子倍增单元，但是电子倍增单元本身被容纳在壳体中以防止周围的空气流动和不被测量的不必要的能量束。
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公开(公告)号：US06707034B1
公开(公告)日：2004-03-16
申请号：US10230349
申请日：2002-08-29
IPC分类号： H01J4926
CPC分类号： H01J49/025
摘要： An ion detector includes an ion input face, a Faraday cup, an ion-to-electron converter dynode, two ion deflection electrodes, an electron multiplier portion, and an anode. The ion input face is formed with an ion input opening. The Faraday cup has an ion collection surface that confronts the ion input opening. The ion-to-electron converter dynode is disposed to one side with respect to the Faraday cup and the ion input opening and has a conversion surface that converts impinging ions into electrons. The two ion deflection electrodes generate an electron lens that attracts and focuses ions from the ion input opening toward the conversion surface of the ion-to-electron converter dynode. The electron multiplier portion receives and multiplies the electrons from the ion-to-electron converter dynode, and includes a plurality of dynodes that multiply electrons one after the other. The plurality of dynodes are juxtaposed in an arc-shape around the Faraday cup. The anode receives electrons from the electron multiplier portion and outputs a signal that corresponds to the amount of input ions.
摘要翻译： 离子检测器包括离子输入面，法拉第杯，离子到电子转换器倍增极，两个离子偏转电极，电子倍增器部分和阳极。 离子输入面由离子输入口形成。 法拉第杯具有面对离子输入口的离子收集表面。 离子 - 电子转换器倍增电极相对于法拉第杯和离子输入开口设置在一侧，并且具有将入射离子转化为电子的转换表面。 两个离子偏转电极产生电子透镜，其吸引并聚焦离子从离子输入开口朝向离子到电子转换器倍增极的转换表面。 电子倍增器部分接收和乘以离子到电子转换器倍增电极的电子，并且包括一个接一个地乘以电子的多个倍增电极。 多个倍增电极以法拉第杯周围的弧形并列。 阳极从电子倍增器部分接收电子，并输出与输入离子量对应的信号。
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公开(公告)号：US20080272947A1
公开(公告)日：2008-11-06
申请号：US11597177
申请日：2004-05-26
申请人： Haruhisa Yamaguchi
发明人： Haruhisa Yamaguchi
摘要： A system clock generator circuit for use in a D/A converter that allows the clock of any frequency to be inputted and also allows usage limiting-conditions to be simplified. A system clock generator circuit for use in a D/A converter for demodulating one-bit digital input data, which has been obtained by ΔΣ modulation scheme, into analog output data in synchronism with an internal system clock and for outputting the analog output data, comprises a counter circuit for receiving external system clocks and LR clocks (LRCLK) having predetermined repetitive frequencies to count the number of the external system clocks included in one period of the LR clocks; a timing generator circuit for generating mask signals for thinning, in accordance with the count value as counted by the counter circuit, the external system clocks at predetermined thinning timings; and a mask circuit for masking the external system clocks by use of the mask signals and thinning the clocks in the masked portions to generate internal system clocks.
摘要翻译： 一种在D / A转换器中使用的系统时钟发生器电路，其允许输入任何频率的时钟，并且还允许简化使用限制条件。 一种用于D / A转换器的系统时钟发生器电路，用于将通过Delta-Sigma调制方案获得的一位数字输入数据与内部系统时钟同步地解调为模拟输出数据，并输出模拟输出数据， 包括用于接收具有预定重复频率的外部系统时钟和LR时钟（LRCLK）的计数器电路，以对包括在LR时钟的一个周期中的外部系统时钟的数量进行计数; 定时发生器电路，用于根据由计数器电路计数的计数值产生用于稀疏的屏蔽信号，外部系统在预定的稀疏定时时钟; 以及掩模电路，用于通过使用掩模信号来屏蔽外部系统时钟，并且对掩蔽部分中的时钟进行稀疏以产生内部系统时钟。
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公开(公告)号：US4105936A
公开(公告)日：1978-08-08
申请号：US686077
申请日：1976-05-13
申请人： Isao Matsumoto , Haruhisa Yamaguchi
发明人： Isao Matsumoto , Haruhisa Yamaguchi
IPC分类号： G11B15/00 , G11B15/06 , G11B15/44 , G11B15/46 , G11B23/04 , G11B23/087 , H02P7/288 , H02P1/04
CPC分类号： G11B15/06 , G11B15/44 , G11B15/46 , G11B23/04 , G11B23/087 , H02P7/2885 , Y10S388/902
摘要： A variable speed tape transport apparatus for a tape cassette wherein the tape is driven at a selected one of plural predetermined speeds. The cassette includes speed indications thereon, each indication representing a respective normal tape speed. These indications are sensed by a sensor which, in turn, controls a control circuit for the tape drive motor such that the tape is selectively driven at a normal relatively lower speed or at a normal relatively higher speed. In addition, a selector mechanism, such as a fast-forward or rewind mechanism, is provided to enable the tape to be driven at a fast speed, this fast speed being at least equal to the relatively higher normal speed.In one embodiment, a tape cassette to be driven at the relatively lower normal speed can be selectively driven at a first higher speed, equal to the relatively higher normal speed, and at a second even higher speed. In this embodiment, a cassette to be driven at the relatively higher normal speed can be selectively driven at the second higher speed.
摘要翻译： 一种用于磁带盒的变速磁带传送装置，其中磁带以选定的多个预定速度驱动。 盒式磁带包括速度指示，每个指示表示相应的正常磁带速度。 这些指示由传感器感测，传感器又控制用于磁带驱动电动机的控制电路，使得磁带以正常的相对较低的速度或正常的相对较高的速度选择性地驱动。 此外，提供了诸如快进或倒退机构的选择机构，以使得能够以快速的速度驱动带，该快速速度至少等于相对较高的正常速度。
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