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1.发明申请CLOCK GENERATOR CIRCUIT FOR SUCCESSIVE APPROXIMATIOM ANALOG TO-DIGITAL CONVERTER 审中-公开时钟发生器电路，用于成功的近似模拟数字转换器公开(公告)号：US20130009796A1
公开(公告)日：2013-01-10
申请号：US13620473
申请日：2012-09-14
IPC分类号： H03M1/38
CPC分类号： H03M1/0624 , H03M1/462
摘要： A sampling clock generator generates a sampling clock based on a reference clock and an internal clock. An internal clock generator causes, during a period in which the sampling clock is at a second voltage level, the internal clock to transition from a first voltage level to a second voltage level when a first comparison signal and a second comparison signal transition to voltage levels different from each other, and the internal clock to transition from the second voltage level to the first voltage level after a variable delay time has elapsed when the first and second comparison signals transition to a same voltage level. A delay controller controls the variable delay time in the internal clock generator so that the ratio of a period in which the sampling clock is at a first voltage level to a period of the reference clock approaches a predetermined ratio.
摘要翻译： 采样时钟发生器基于参考时钟和内部时钟生成采样时钟。 当第一比较信号和第二比较信号转换到电压电平时，内部时钟发生器在采样时钟处于第二电压电平的时段期间使内部时钟从第一电压电平转变到第二电压电平 并且当第一和第二比较信号转变到相同电压电平时，在经过可变延迟时间之后，内部时钟从第二电压电平转变到第一电压电平。 延迟控制器控制内部时钟发生器中的可变延迟时间，使得采样时钟处于第一电压电平的周期与参考时钟的周期之间的比率接近预定比率。
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公开(公告)号：US07808295B2
公开(公告)日：2010-10-05
申请号：US12296021
申请日：2007-06-15
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。 给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号 包括在该电平移位器中的晶体管（Mn1）是相位量X（0°
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公开(公告)号：US20090134931A1
公开(公告)日：2009-05-28
申请号：US12296021
申请日：2007-06-15
IPC分类号： H03L5/00
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。 给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号 包括在该电平移位器中的晶体管（Mn1）是相位量X（0°
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公开(公告)号：US20080315933A1
公开(公告)日：2008-12-25
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K3/00
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。
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公开(公告)号：US07920002B2
公开(公告)日：2011-04-05
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K5/01
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。
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6.发明授权Reference frequency generation circuit, semiconductor integrated circuit, and electronic device 有权参考频率发生电路，半导体集成电路和电子设备公开(公告)号：US08212624B2
公开(公告)日：2012-07-03
申请号：US13022029
申请日：2011-02-07
IPC分类号： H02K3/26
CPC分类号： H03K4/501
摘要： An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.
摘要翻译： 响应于参考时钟的信号电平的转变，振荡器电路以互补的方式增加并降低第一和第二振荡信号的信号电平。 振荡控制电路将第一和第二振荡信号的每个信号电平与比较电压进行比较，并根据比较结果使参考时钟的信号电平转变。 参考控制电路增加或减小比较电压，使得与第一和第二振荡信号的相应摆动成比例的中间信号的信号电平与参考电压之间的差减小。
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公开(公告)号：US08130608B2
公开(公告)日：2012-03-06
申请号：US12967498
申请日：2010-12-14
CPC分类号： H03K3/0315 , H03K2005/00052
摘要： In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
摘要翻译： 在包括q个环形振荡器的耦合环形振荡器中，每个环形振荡器包括连接在一起以形成环形的p个反相器电路，以及包括（p×q）个相位耦合电路的相位耦合环，每个相位耦合电路被配置为耦合p的一个的输出 q环振荡器中的一个的逆变器电路以预定的相位关系连接到另一个q个环形振荡器的p个反相器电路之一的输出，并且连接在一起以形成环形，用于至少一个组 每个q环振荡器中的p个反相器电路中的一个的上升，属于至少一个组的q个反相器电路的输出彼此相位固定，使q个环形振荡器在同相中振荡 固定状态，然后将q个逆变器电路的输出从同相固定状态解除。
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公开(公告)号：US20110080821A1
公开(公告)日：2011-04-07
申请号：US12967498
申请日：2010-12-14
CPC分类号： H03K3/0315 , H03K2005/00052
摘要： In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
摘要翻译： 在包括q个环形振荡器的耦合环形振荡器中，每个环形振荡器包括连接在一起以形成环形的p个反相器电路，以及包括（p×q）个相位耦合电路的相位耦合环，每个相位耦合电路被配置为耦合p的一个的输出 q环振荡器中的一个的逆变器电路以预定的相位关系连接到另一个q个环形振荡器的p个反相器电路之一的输出，并且连接在一起以形成环形，用于至少一个组 每个q环振荡器中的p个反相器电路中的一个的上升，属于至少一个组的q个反相器电路的输出彼此相位固定，使q个环形振荡器在同相中振荡 固定状态，然后将q个逆变器电路的输出从同相固定状态解除。
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公开(公告)号：US07782112B2
公开(公告)日：2010-08-24
申请号：US12330947
申请日：2008-12-09
IPC分类号： G06F1/04
CPC分类号： H03K5/135 , H03K5/1565 , H03K23/54 , H03K2005/00241
摘要： In a device for generating a clock signal having a desired phase from input multi-phase clock signals, an intermediate clock generator generates, by using one of the input multi-phase clock signals as a reference clock signal, multi-phase intermediate clock signals in which one cycle is equal to a plurality of cycles of the reference clock signal. A first phase selector selects one of the multi-phase intermediate clock signals. A second phase selector selects one of the multi-phase clock signals. A latch circuit latches the intermediate clock signal selected by the first phase selector with the clock signal selected by the second phase selector.
摘要翻译： 在用于从输入多相时钟信号产生期望相位的时钟信号的装置中，中间时钟发生器通过使用输入多相时钟信号之一作为参考时钟信号来产生多相中间时钟信号 哪个周期等于参考时钟信号的多个周期。 第一相位选择器选择多相中间时钟信号之一。 第二相位选择器选择多相时钟信号之一。 锁存电路将由第一相位选择器选择的中间时钟信号与由第二相位选择器选择的时钟信号进行锁存。
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公开(公告)号：US20100225518A1
公开(公告)日：2010-09-09
申请号：US12376400
申请日：2007-06-19
申请人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Kurumi Nakayama
发明人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Kurumi Nakayama
IPC分类号： H03M1/66
CPC分类号： G09G3/3685 , G09G3/3696 , G09G2310/027 , H03M1/76
摘要： A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).
摘要翻译： 选择部（105）选择与数字数据（D-DATA）的数字值对应的，具有逐步变化的电压值的多个阶梯电压（SV1，SV2，SV3 ......等）中的阶梯电压。 对于多个步进电压（SV1，SV2，SV3 ...）中的每一个，将不同的数字值分配给步进电压的不同步骤。 放大器部分（106）放大由选择部分（105）选择的步进电压。 输出部分（107）输出由放大器部分（106）放大的阶跃电压作为对应于数字数据（D-DATA）的数字值的时间周期的输出电压（Vout）。
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