公开(公告)号：US08692701B2

公开(公告)日：2014-04-08

申请号：US13599195

申请日：2012-08-30

Applicant: Shoji Kawahito ,  Sung Wook Jung ,  Osamu Kobayashi ,  Yasuhide Shimizu ,  Takahiro Miki ,  Takashi Morie ,  Hirotomo Ishii

Inventor： Shoji Kawahito ,  Sung Wook Jung ,  Osamu Kobayashi ,  Yasuhide Shimizu ,  Takahiro Miki ,  Takashi Morie ,  Hirotomo Ishii

IPC: H03M1/38

CPC classification number: H03M1/06 ,  H03M1/167

Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

Abstract translation: 流水线A / D转换器电路包括：采样保持电路，被配置为采样和保持模拟输入信号，并输出采样保持信号;以及A / D转换器电路，包括级联地彼此连接的A / D转换器电路部分， 并以流水线形式执行A / D转换。 每级的流水线A / D转换器电路部分包括子A / D转换器电路，乘法器D / A转换器电路和预充电电路。 子A / D转换电路包括比较器，A / D将输入信号转换为预定位的数字信号; D / A转换器电路，用于对来自子A / D转换器的数字信号进行D / A转换 电路作为参考电压产生的模拟控制信号作为参考值，通过基于模拟控制信号的采样电容进行采样，保持和放大输入信号。

公开(公告)号：US20130057418A1

公开(公告)日：2013-03-07

申请号：US13599195

申请日：2012-08-30

Applicant: Shoji KAWAHITO ,  Sung Wook JUNG ,  Osamu KOBAYASHI ,  Yasuhide SHIMIZU ,  Takahiro MIKI ,  Takashi MORIE ,  Hirotomo ISHII

Inventor： Shoji KAWAHITO ,  Sung Wook JUNG ,  Osamu KOBAYASHI ,  Yasuhide SHIMIZU ,  Takahiro MIKI ,  Takashi MORIE ,  Hirotomo ISHII

IPC: H03M1/12

CPC classification number: H03M1/06 ,  H03M1/167

Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

Abstract translation: 流水线A / D转换器电路包括：采样保持电路，被配置为采样和保持模拟输入信号，并输出采样保持信号;以及A / D转换器电路，包括级联地彼此连接的A / D转换器电路部分， 并以流水线形式执行A / D转换。 每级的流水线A / D转换器电路部分包括子A / D转换器电路，乘法器D / A转换器电路和预充电电路。 子A / D转换电路包括比较器，A / D将输入信号转换为预定位的数字信号; D / A转换器电路，用于对来自子A / D转换器的数字信号进行D / A转换 电路作为参考电压产生的模拟控制信号作为参考值，通过基于模拟控制信号的采样电容采样，保持和放大输入信号。

公开(公告)号：US07920002B2

公开(公告)日：2011-04-05

申请号：US12133901

申请日：2008-06-05

Applicant: Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

Inventor： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

IPC: H03K5/01

CPC classification number: H03K5/00006 ,  H03K5/13

Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Abstract translation: n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

公开(公告)号：US07633421B2

公开(公告)日：2009-12-15

申请号：US12093252

申请日：2007-07-30

Applicant: Shiro Dosho ,  Takashi Morie ,  Yusuke Tokunaga ,  Shiro Sakiyama

Inventor： Shiro Dosho ,  Takashi Morie ,  Yusuke Tokunaga ,  Shiro Sakiyama

IPC: H03M1/12

CPC classification number: H03M1/123 ,  H03M1/1215 ,  H03M1/56

Abstract: An A/D converter includes: a plurality of A/D conversion circuits (10 a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.

Abstract translation: A / D转换器包括：多个A / D转换电路（10a，10b）; 输入选择部分（20），用于选择不执行A / D转换的A / D转换电路以提供通过采样保持输入信号获得的模拟量; 以及用于选择不执行A / D转换的A / D转换电路以输出从所选择的数字量获得的数字量的输出选择部分（30）。 每个A / D转换电路包括：用于在多个模拟存储器元件（111）中顺序地存储所提供的模拟量的输入存储器部分（11）。 具有用于将存储在模拟存储器元件中的模拟量转换为数字量的多个A / D转换元件的A / D转换部分（12） 以及移位输出部分（13），具有从A / D转换元件接收数字量以保持数字量的多个寄存器（131），用于移位和输出保存在寄存器中的数字量。

公开(公告)号：US20090284282A1

公开(公告)日：2009-11-19

申请号：US12510718

申请日：2009-07-28

Applicant: Akinori MATSUMOTO ,  Shiro Sakiyama ,  Takashi Morie

Inventor： Akinori MATSUMOTO ,  Shiro Sakiyama ,  Takashi Morie

IPC: H03K19/0175 ,  H03L5/00

CPC classification number: H03K3/35613

Abstract: Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.

Abstract translation: 输入晶体管具有连接到输入一对输入信号的第一输入参考节点和栅极的源极。 输入侧电压松弛晶体管具有连接到一对输入晶体管的漏极和连接到第二输入参考节点的栅极的源极。 输出侧电压松弛晶体管具有连接到输出节点的源极，连接到第一输出参考节点的栅极和连接到输入侧电压松弛晶体管的漏极的漏极。 第一和第二反相器电路与输出节点对应，并连接在第二和第三输出参考节点之间。 第一和第二反相器电路中的每一个还根据其非对应的输出节点之间的电压将第二和第三输出参考节点中的一个上的电压提供给其对应的一个输出节点。

公开(公告)号：US20080169948A1

公开(公告)日：2008-07-17

申请号：US11792081

申请日：2005-09-02

Applicant: Kouji Okamoto ,  Takashi Morie ,  Shiro Dosho ,  Hirokuni Fujiyama

Inventor： Kouji Okamoto ,  Takashi Morie ,  Shiro Dosho ,  Hirokuni Fujiyama

IPC: H03M1/06 ,  H03H11/04 ,  H03H11/20 ,  H03M1/10 ,  H03H11/12

CPC classification number: H03G5/16 ,  H03H11/1291 ,  H03H11/20

Abstract: In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2. As a result, variations in the response characteristics of the Gm-C filter 2 are adjusted with high accuracy with a simple circuit structure.

Abstract translation: 在用于诸如Gm-C滤波器的模拟滤波器电路的滤波器调节电路中，来自参考信号产生电路1的输入信号IS被输入到要过滤的Gm-C滤波器2，然后由转换电路3转换成 数字信号。 来自参考信号发生电路1的参考信号RS由转换电路4转换成数字信号。 两个转换信号在保持电路5中保持时间序列。定时产生电路6基于来自保持电路5的基准时间序列信号ref产生更新定时信号en。控制信号产生电路7产生控制 基于参考时间序列信号ref的信号CS和来自保持电路5的滤波器输出时间序列信号tgt。控制信号CS响应于更新定时信号en至...而被输入到Gm-C滤波器2 调整Gm-C滤波器2的增益。结果，以简单的电路结构，高精度地调整Gm-C滤波器2的响应特性的变化。

公开(公告)号：US07298219B2

公开(公告)日：2007-11-20

申请号：US11269742

申请日：2005-11-09

Applicant: Shiro Dosho ,  Takashi Morie ,  Kouji Okamoto ,  Yuji Yamada ,  Kazuaki Sogawa

Inventor： Shiro Dosho ,  Takashi Morie ,  Kouji Okamoto ,  Yuji Yamada ,  Kazuaki Sogawa

IPC: H03L7/00 ,  H03L1/02

CPC classification number: H03L7/0995 ,  H03L7/0898 ,  H03L7/18 ,  H03L7/1976

Abstract: The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.

Abstract translation: 锁相环电路包括用于设定压控振荡器的增益的增益设定电路和用于设定时间常数的时间常数设定电路，时间常数由电荷泵电路中的电流量和电容 环路滤波器的值。 增益设定电路将增益设定为预定值，时间常数设定电路将时间常数设定为规定值，由此将锁相环电路的环带宽度设定为期望值。

公开(公告)号：US20060206555A1

公开(公告)日：2006-09-14

申请号：US11434779

申请日：2006-05-17

Applicant: Osamu Nomura ,  Takashi Morie ,  Teppei Nakano

Inventor： Osamu Nomura ,  Takashi Morie ,  Teppei Nakano

IPC: G06F7/38

CPC classification number: G06N3/049 ,  G06N3/063 ,  H03K7/08 ,  H03K9/08 ,  H03M5/08

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n−1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract translation: 产品总和运算电路包括将具有表示操作数值的脉冲宽度的脉冲信号转换为数字信号的脉冲宽度/数字转换电路（9），分选电路（4），按照下列或者升序排列 由脉冲宽度/数字转换电路（9）转换为数字信号的多个操作数值Xi以及将从分选电路（4）输出的每个操作数值乘以相应的操作数值的累积和电路（1） Wi并计算乘积结果的累加和。 脉冲宽度/数字转换电路（9）包括对时钟进行计数的计数器（10），并输出作为数字信号的计数值，以及n个后沿锁存电路（11〜0-11〜（n-1）） 其在输入脉冲信号的后沿锁存从计数器输出的公共计数值。

公开(公告)号：US20050138100A1

公开(公告)日：2005-06-23

申请号：US11055283

申请日：2005-02-10

Applicant: Osamu Nomura ,  Takashi Morie ,  Keisuke Korekado

Inventor： Osamu Nomura ,  Takashi Morie ,  Keisuke Korekado

IPC: G06F7/24 ,  G06F7/38 ,  G06F7/544 ,  G06F17/10 ,  G06N3/063

CPC classification number: G06F7/5443 ,  G06N3/063

Abstract: A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results.

Abstract translation: 产品和运算电路包括输出多个操作数值x1，x2，...的排序块（4）。 。 。 xi按照降序或升序排列;以及操作单元（1），其将从分类块（4）输出的每个操作数值xi乘以相应的操作数值Wi，并计算乘法结果的累加和。

公开(公告)号：US20050122238A1

公开(公告)日：2005-06-09

申请号：US11036001

申请日：2005-01-18

Applicant: Osamu Nomura ,  Takashi Morie ,  Teppei Nakano

Inventor： Osamu Nomura ,  Takashi Morie ,  Teppei Nakano

IPC: G06F7/544 ,  G06N3/04 ,  G06N3/063 ,  H03K7/08 ,  H03K9/08 ,  H03M1/82 ,  H03M5/08

CPC classification number: G06N3/049 ,  G06N3/063 ,  H03K7/08 ,  H03K9/08 ,  H03M5/08

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n−1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract translation: 产品总和运算电路包括将具有表示操作数值的脉冲宽度的脉冲信号转换为数字信号的脉冲宽度/数字转换电路（9），分选电路（4），按照下列或者升序排列 由脉冲宽度/数字转换电路（9）转换为数字信号的多个操作数值Xi以及将从分选电路（4）输出的每个操作数值乘以相应的操作数值的累积和电路（1） Wi并计算乘积结果的累加和。 脉冲宽度/数字转换电路（9）包括对时钟进行计数并输出计数值作为数字信号的计数器（10），以及n个后沿锁存电路（11 - 0 - 11 - （n- 1）） 其在输入脉冲信号的后沿锁存从计数器输出的公共计数值。