公开(公告)号：US07493438B2

公开(公告)日：2009-02-17

申请号：US09971211

申请日：2001-10-03

申请人： Shivnandan D. Kaushik ,  James B. Crossland ,  Mohan J. Kumar ,  Linda J. Rankin ,  David J. O'Shea

发明人： Shivnandan D. Kaushik ,  James B. Crossland ,  Mohan J. Kumar ,  Linda J. Rankin ,  David J. O'Shea

IPC分类号： G06F13/00

CPC分类号： G06F13/4081

摘要： An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.

摘要翻译： 描述了在计算节点的热插拔期间枚举处理器的装置和方法。 该方法包括响应于热插拔复位的一个或多个处理器的枚举。 枚举被提供给其中计算节点被热插拔的系统架构操作系统。 枚举完成后，响应于操作系统激活请求启动计算节点。 因此，一旦设备枚举以及资源枚举完成，处理器存储器节点的一个或多个处理器被激活，使得操作系统可以开始利用热插拔的计算节点的处理器。

公开(公告)号：US07117311B1

公开(公告)日：2006-10-03

申请号：US10027397

申请日：2001-12-19

申请人： Linda J. Rankin ,  Shivnandan D. Kaushik ,  James B. Crossland ,  Mohan J. Kumar ,  David J. O'Shea

发明人： Linda J. Rankin ,  Shivnandan D. Kaushik ,  James B. Crossland ,  Mohan J. Kumar ,  David J. O'Shea

IPC分类号： G06F13/00

CPC分类号： G06F12/0822 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0831

摘要： A computing device maintains coherency while supporting addition and removal of memory caching agents without rebooting the computing device.

摘要翻译： 计算设备维护一致性，同时支持添加和删除内存高速缓存代理，而无需重新启动计算设备。

公开(公告)号：US07673090B2

公开(公告)日：2010-03-02

申请号：US10028858

申请日：2001-12-19

申请人： Shivnandan D. Kaushik ,  Ling Cen ,  James B. Crossland ,  Mohan J. Kumar ,  Linda J. Rankin ,  David J. O'Shea

发明人： Shivnandan D. Kaushik ,  Ling Cen ,  James B. Crossland ,  Mohan J. Kumar ,  Linda J. Rankin ,  David J. O'Shea

IPC分类号： H05K7/10 ,  G06F13/24 ,  G06F13/32 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/4081

摘要： Hot plug modules comprising processors, memory, and/or I/O hubs may be added to and removed from a running computing device without rebooting the running computing device. The hot plug modules and computing device comprise hot plug interfaces that support hot plug addition and hot plug removal of the hot plug modules.

摘要翻译： 包括处理器，存储器和/或I / O集线器的热插拔模块可以被添加到正在运行的计算设备和从运行的计算设备移除，而不需要重新启动正在运行的计算设备。 热插拔模块和计算设备包括热插拔接口，其支持热插拔模块和热插拔模块的热插拔。

公开(公告)号：US07822900B2

公开(公告)日：2010-10-26

申请号：US12271725

申请日：2008-11-14

申请人： Shivnandan D. Kaushik ,  James B. Crossland ,  Mohan J. Kumar ,  Linda J. Rankin ,  David J. O'Shea

发明人： Shivnandan D. Kaushik ,  James B. Crossland ,  Mohan J. Kumar ,  Linda J. Rankin ,  David J. O'Shea

IPC分类号： G06F13/00

CPC分类号： G06F13/4081

摘要： An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.

摘要翻译： 描述了在计算节点的热插拔期间枚举处理器的装置和方法。 该方法包括响应于热插拔复位的一个或多个处理器的枚举。 枚举被提供给其中计算节点被热插拔的系统架构操作系统。 枚举完成后，响应于操作系统激活请求启动计算节点。 因此，一旦设备枚举以及资源枚举完成，处理器存储器节点的一个或多个处理器被激活，使得操作系统可以开始利用热插拔的计算节点的处理器。

公开(公告)号：US20090106471A1

公开(公告)日：2009-04-23

申请号：US12271725

申请日：2008-11-14

申请人： Shivnandan D. Kaushik ,  James B. Crossland ,  Mohan J. Kumar ,  Linda J. Rankin ,  David J. O'Shea

发明人： Shivnandan D. Kaushik ,  James B. Crossland ,  Mohan J. Kumar ,  Linda J. Rankin ,  David J. O'Shea

IPC分类号： G06F13/00

CPC分类号： G06F13/4081

摘要： An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.

摘要翻译： 描述了在计算节点的热插拔期间枚举处理器的装置和方法。 该方法包括响应于热插拔复位的一个或多个处理器的枚举。 枚举被提供给其中计算节点被热插拔的系统架构操作系统。 枚举完成后，响应于操作系统激活请求启动计算节点。 因此，一旦设备枚举以及资源枚举完成，处理器存储器节点的一个或多个处理器被激活，使得操作系统可以开始利用热插拔的计算节点的处理器。

公开(公告)号：US07000102B2

公开(公告)日：2006-02-14

申请号：US09895580

申请日：2001-06-29

申请人： Mohan J. Kumar ,  Shivnandan D. Kaushik ,  James B. Crossland ,  Linda J. Rankin ,  David J. O'Shea

发明人： Mohan J. Kumar ,  Shivnandan D. Kaushik ,  James B. Crossland ,  Linda J. Rankin ,  David J. O'Shea

IPC分类号： G06F9/445 ,  G06F1/26

CPC分类号： G06F1/30 ,  G06F1/3203 ,  G06F9/4418

摘要： One aspect of the invention relates to a method for supporting hibernation despite the presence of hot-plugged nodes and non-deterministic boot operations. The method comprises invoking a management interrupt in response to a Hibernate request. The management interrupt is used to obtain and store platform configuration information into a non-volatile storage location. The platform configuration information includes data to indicate whether a next boot sequence for a platform occurs as a deterministic boot sequence or a non-deterministic boot sequence as well as a boot node identifier and a listing of an order in which processors of the platform are initialized.

公开(公告)号：US06917999B2

公开(公告)日：2005-07-12

申请号：US09895692

申请日：2001-06-29

申请人： Mohan J. Kumar ,  Shivnandan D. Kaushik ,  James B. Crossland ,  Linda J. Rankin ,  David J. O'Shea

发明人： Mohan J. Kumar ,  Shivnandan D. Kaushik ,  James B. Crossland ,  Linda J. Rankin ,  David J. O'Shea

IPC分类号： G06F9/445 ,  G06F9/50 ,  G06F13/00

CPC分类号： G06F9/5077 ,  G06F9/4411

摘要： One aspect of the invention relates to creation of a container object being part of software that is stored in platform readable medium and executed by a processor within a platform. The container comprises (i) a hardware identification object to identify to an operating system of the platform that a type of device represented by the container object is a node and (ii) a plurality of component objects to identify constituent components of the node. Another aspect of the invention is the distribution of BIOS to handle initiation of components of a substrate in response to hot-plug addition of that substrate.

摘要翻译： 本发明的一个方面涉及作为存储在平台可读介质中并由平台内的处理器执行的软件的一部分的容器对象的创建。 容器包括（i）用于向平台的操作系统识别由容器对象表示的设备的类型是节点的硬件标识对象，以及用于识别节点的组成部件的多个组件对象。 本发明的另一方面是响应于该基板的热插入添加而分配BIOS以处理基板的部件的启动。

公开(公告)号：US07376775B2

公开(公告)日：2008-05-20

申请号：US10749929

申请日：2003-12-29

申请人： Lily Pao Looi ,  Stanley Steven Kulick ,  Dean A Mulla ,  Ashish Gupta ,  Keith R. Pflederer ,  Shivnandan D. Kaushik ,  Mohan J. Kumar ,  James B. Crossland

发明人： Lily Pao Looi ,  Stanley Steven Kulick ,  Dean A Mulla ,  Ashish Gupta ,  Keith R. Pflederer ,  Shivnandan D. Kaushik ,  Mohan J. Kumar ,  James B. Crossland

IPC分类号： G06F13/00

CPC分类号： G06F11/1666 ,  G06F13/16

摘要： In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.

摘要翻译： 在一些实施例中，一种装置包括处理器，扩展器存储器桥位置，耦合到扩展器存储器桥位置的存储器，以及总线控制器，其包括拦截和阻止从处理器到扩展器存储器桥位置的通信的截距逻辑，并且模拟 一个扩展记忆桥。 在一些实施例中，一种方法包括拦截和阻止对设备的状态请求，而不管该设备是否被安装，以及响应状态请求。

公开(公告)号：US07627706B2

公开(公告)日：2009-12-01

申请号：US11850782

申请日：2007-09-06

申请人： Shivnandan D. Kaushik ,  Keshavan K. Tiruvallur ,  James B. Crossland ,  Sridhar Muthrasanallur ,  Rajesh S. Parthasarathy ,  Luke P. Hood

发明人： Shivnandan D. Kaushik ,  Keshavan K. Tiruvallur ,  James B. Crossland ,  Sridhar Muthrasanallur ,  Rajesh S. Parthasarathy ,  Luke P. Hood

IPC分类号： G06F13/24 ,  G06F13/32

CPC分类号： G06F13/24

摘要： In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.

摘要翻译： 在一些实施例中，装置包括用于接收物理处理器标识号的逻辑中断识别号码创建逻辑，并通过使用物理处理器标识号创建逻辑处理器标识号。 每个逻辑处理器识别号对应于物理处理器识别号之一，并且逻辑处理器标识号各自包括处理器群标识号和群内标识号。 每个处理器集群标识号被形成为包括从相应的物理处理器标识号码位置移位的一组位，并且群内标识号分别响应于对应的物理处理器标识的其他位的值而形成 数。 描述其他实施例。

公开(公告)号：US20090070511A1

公开(公告)日：2009-03-12

申请号：US11850790

申请日：2007-09-06

申请人： Shivnandan D. Kaushik ,  Keshavan K. Tiruvallur ,  James B. Crossland ,  Sridhar Muthrasanallur ,  Rajesh S. Parthasarathy ,  Luke P. Hood

发明人： Shivnandan D. Kaushik ,  Keshavan K. Tiruvallur ,  James B. Crossland ,  Sridhar Muthrasanallur ,  Rajesh S. Parthasarathy ,  Luke P. Hood

IPC分类号： G06F13/24

CPC分类号： G06F9/505 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/5094 ,  G06F13/24 ,  Y02D10/14 ,  Y02D10/22

摘要： In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.

摘要翻译： 在一些实施例中，一种装置包括处理器选择逻辑，以接收与每个具有处理器集群标识号的中断相关联的逻辑目的地标识号，以识别中断指向的处理器的集群。 逻辑目的地识别号码各自用于识别所识别的处理器簇内的哪些处理器可用于接收相应的一个中断。 处理器选择逻辑是选择一个可用的处理器来接收中断，并且通过逻辑目的地标识号中的对应位的相对位置来识别所选择的一个可用处理器。 描述其他实施例。