公开(公告)号：US07303950B2

公开(公告)日：2007-12-04

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下面形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US20050156242A1

公开(公告)日：2005-07-21

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

公开(公告)号：US06461935B2

公开(公告)日：2002-10-08

申请号：US09989152

申请日：2001-11-21

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor device having a trench-shaped isolator, adjacent to the semiconductor element region is formed having a width which is continuously decreased in the downward direction for relaxing the stress in the silicon layer. Embodiments include forming a patterned dielectric layer on an SOI substrate, forming sidewall spacers thereon, and etching the underlying silicon layer followed by oxidation or controlled etching to form the trench with downwardly decreasing side surfaces.

摘要翻译： 具有与半导体元件区域相邻的沟槽形隔离器的半导体器件形成为具有在向下方向上连续减小的宽度，以缓解硅层中的应力。 实施例包括在SOI衬底上形成图案化的电介质层，在其上形成侧壁间隔物，并蚀刻下面的硅层，接着进行氧化或受控蚀刻，以形成具有向下减少的侧表面的沟槽。

公开(公告)号：US06372599B1

公开(公告)日：2002-04-16

申请号：US09371027

申请日：1999-08-10

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The invention provides a semiconductor device having the trench-shaped isolator is provided with a portion which is adjacent to the semiconductor element region, of which the width is continuously decreased in the downward direction, and of which the surface is planarized near the semiconductor element region, for relaxing the stress in the silicon layer and being flat the surface of the trench-shaped insulator, and method of manufacturing the same.

公开(公告)号：US06953979B1

公开(公告)日：2005-10-11

申请号：US09466934

申请日：1999-12-20

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下方形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的下部并排形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US06879002B2

公开(公告)日：2005-04-12

申请号：US10431473

申请日：2003-05-08

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L27/12 ,  H01L29/423 ,  H01L31/0392 ,  H01L27/01 ,  H01L29/00

CPC分类号： H01L27/1203 ,  H01L29/42384

摘要： A semiconductor device comprising an SOI substrate fabricated by forming a silicon layer 3 on an insulating layer 2, a plurality of active regions 3 horizontally arranged in the silicon layer 3, and element isolating parts 5 having a trench-like shape which is made of an insulator 5 embedded between the active regions 3 in the silicon layer 3, wherein the insulating layer 2 has spaces 6 positioned in the vicinity of interfaces between the active regions and the element isolating parts 5, whereby it becomes possible to reduce fixed charges or holes existing on a side of the insulating layer in interfaces between the silicon layer and the insulating layer, which fixed charges or holes are generated in a process of oxidation for forming the insulating layer on a bottom surface of the silicon layer.

摘要翻译： 一种半导体器件，包括通过在绝缘层2上形成硅层3，在硅层3中水平布置的多个有源区3和由沟槽状构成的沟槽状形状的元件隔离部5制造的SOI衬底 绝缘体5嵌入在硅层3中的有源区3之间，其中绝缘层2具有位于有源区和元件隔离部5之间的界面附近的空间6，从而可以减少固定电荷或孔 在硅层和绝缘层之间的界面中的绝缘层的一侧上，在硅层的底表面上形成绝缘层的氧化过程中产生固定的电荷或空穴。

公开(公告)号：US06586802B2

公开(公告)日：2003-07-01

申请号：US09346726

申请日：1999-07-02

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2701

CPC分类号： H01L27/1203 ,  H01L29/42384

摘要： A semiconductor device comprising an SOI substrate fabricated by forming a silicon layer 3 on an insulating layer 2, a plurality of active regions 3 horizontally arranged in the silicon layer 3, and element isolating parts 5 having a trench-like shape which is made of an insulator 5 embedded between the active regions 3 in the silicon layer 3, wherein the insulating layer 2 has spaces 6 positioned in the vicinity of interfaces between the active regions and the element isolating parts 5, whereby it becomes possible to reduce fixed charges or holes existing on a side of the insulating layer in interfaces between the silicon layer and the insulating layer, which fixed charges or holes are generated in a process of oxidation for forming the insulating layer on a bottom surface of the silicon layer.

摘要翻译： 一种半导体器件，包括通过在绝缘层2上形成硅层3，在硅层3中水平布置的多个有源区3和由沟槽状构成的沟槽状形状的元件隔离部5制造的SOI衬底 绝缘体5嵌入在硅层3中的有源区域3之间，其中绝缘层2具有位于有源区域和元件隔离部分5之间的界面附近的空间6，由此可以减少固定电荷或存在的孔 在硅层和绝缘层之间的界面中的绝缘层的一侧上，在硅层的底表面上形成绝缘层的氧化过程中产生固定的电荷或空穴。

公开(公告)号：US06271065B1

公开(公告)日：2001-08-07

申请号：US09494352

申请日：2000-01-31

申请人： Shoichi Miyamoto ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Takashi Ipposhi

IPC分类号： H01L2100

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78636

摘要： On an insulating film a mesa-isolation silicon layer is formed, in which a channel region and source/drain regions ar included. A gate insulating film and a conducting layer as a part of a gate electrode are stacked on the mesa-isolation silicon layer. A sidewall of an insulating material is formed on side surfaces of the mesa-isolation silicon layer, gate insulating film, and conducting layer at an end portion of the channel region of the mesa-isolation silicon layer, and a gate electrode is formed on the conducting layer.

摘要翻译： 在绝缘膜上形成台状隔离硅层，其中包括沟道区和源极/漏极区。 栅极绝缘膜和作为栅电极的一部分的导电层堆叠在台面隔离硅层上。 在台面隔离硅层的沟道区的端部的台面隔离硅层，栅极绝缘膜和导电层的侧面形成绝缘材料的侧壁，在 导电层。

公开(公告)号：US06225148B1

公开(公告)日：2001-05-01

申请号：US09221121

申请日：1998-12-28

申请人： Shoichi Miyamoto ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Takashi Ipposhi

IPC分类号： H01C2100

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L29/4908

摘要： A method of fabricating an SOIMOS transistor, isolated by trench isolation, which can prevent a gate oxide film from dielectric breakdown on peripheral edge portions of an SOI layer while preventing formation of parasitic MOS transistors on the peripheral edge portions of the SOI layer under a gate electrode is provided. A nitride film (6) is removed with phosphoric acid of about 160° C. in temperature and thereafter a polysilicon film (5) is removed by isotropic dry etching, thereby leaving a pad oxide film (4) and side wall oxide films (7) in a state enclosed with a deposition oxide film (8). Thereafter the pad oxide film (4), the side wall oxide films (7) and the deposition oxide film (8) are simultaneously removed with hydrofluoric acid.

摘要翻译： 一种制造通过沟槽隔离隔离的SOIMOS晶体管的方法，其可以防止栅极氧化膜在SOI层的外围边缘部分上的介质击穿，同时防止在栅极下的SOI层的外围边缘部分上形成寄生MOS晶体管 提供电极。 用温度约160℃的磷酸除去氮化物膜（6），然后通过各向同性干蚀刻除去多晶硅膜（5），由此留下衬垫氧化膜（4）和侧壁氧化膜（7 ）处于以沉积氧化膜（8）包围的状态。 此后，用氢氟酸同时除去衬垫氧化膜（4），侧壁氧化物膜（7）和沉积氧化物膜（8）。

公开(公告)号：US6064090A

公开(公告)日：2000-05-16

申请号：US671542

申请日：1996-06-27

申请人： Shoichi Miyamoto ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Takashi Ipposhi

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78636

摘要： On an insulating film a mesa-isolation silicon layer is formed, in which a channel region and source/drain regions are included. A gate insulating film and a conducting layer as a part of a gate electrode are stacked on the mesa-isolation silicon layer. A sidewall of an insulating material is formed on side surfaces of the mesa-isolation silicon layer, gate insulating film, and conducting layer at an end portion of the channel region of the mesa-isolation silicon layer, and a gate electrode is formed on the conducting layer.

摘要翻译： 在绝缘膜上形成台面隔离硅层，其中包括沟道区和源极/漏极区。 栅极绝缘膜和作为栅电极的一部分的导电层堆叠在台面隔离硅层上。 在台面隔离硅层的沟道区的端部的台面隔离硅层，栅极绝缘膜和导电层的侧面形成绝缘材料的侧壁，在 导电层。