公开(公告)号：US07601603B2

公开(公告)日：2009-10-13

申请号：US11094782

申请日：2005-03-31

申请人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Tomoatsu Makino ,  Syouji Nogami ,  Tomonori Yamaoka

发明人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Tomoatsu Makino ,  Syouji Nogami ,  Tomonori Yamaoka

IPC分类号： H01L21/20

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L29/0634 ,  H01L29/7811

摘要： A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底中形成沟槽; 以及在包括沟槽的侧壁和底部的衬底上形成外延膜，使得外延膜填充在沟槽中。 形成外延膜的步骤包括在沟槽被外延膜填充之前的最后步骤。 最终步骤具有外延膜的形成条件，使得形成在沟槽的侧壁上的外延膜在沟槽的开口处的生长速率小于沟槽位置处的生长速率， 其比沟槽的开口更深。

公开(公告)号：US20080001261A1

公开(公告)日：2008-01-03

申请号：US11847656

申请日：2007-08-30

申请人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi

发明人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi

IPC分类号： H01L29/06 ,  H01L21/20

CPC分类号： H01L29/861 ,  H01L29/0634 ,  H01L29/6609

摘要： In order to suppress deterioration in charge balance and maintain excellent withstand voltage characteristics after forming a super junction structure on a semiconductor substrate, a plurality of columnar first epitaxial layers are respectively formed on a surface of a substrate main body at predetermined intervals, and a plurality of second epitaxial layers are respectively formed in trenches between the plurality of first epitaxial layers. A concentration distribution of a dopant included in the first epitaxial layer in a surface parallel with the surface of the substrate main body is configured to match with a concentration distribution of a dopant included in the second epitaxial layer in a surface parallel with the surface of the substrate main body.

摘要翻译： 为了抑制电荷平衡的劣化，并且在半导体衬底上形成超结结构之后保持优异的耐电压特性，多个柱状第一外延层分别以预定间隔分别形成在衬底主体的表面上，并且多个 的第二外延层分别形成在多个第一外延层之间的沟槽中。 在与基板主体的表面平行的表面中包含在第一外延层中的掺杂剂的浓度分布被配置为与包含在第二外延层中的掺杂剂的浓度分布在与 基板主体。

公开(公告)号：US20070108444A1

公开(公告)日：2007-05-17

申请号：US11383782

申请日：2006-05-17

申请人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi

发明人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi

IPC分类号： C30B29/66

CPC分类号： H01L29/861 ,  H01L29/0634 ,  H01L29/6609

摘要： In order to suppress deterioration in charge balance and maintain excellent withstand voltage characteristics after forming a super junction structure on a semiconductor substrate, a plurality of columnar first epitaxial layers are respectively formed on a surface of a substrate main body at predetermined intervals, and a plurality of second epitaxial layers are respectively formed in trenches between the plurality of first epitaxial layers. A concentration distribution of a dopant included in the first epitaxial layer in a surface parallel with the surface of the substrate main body is configured to match with a concentration distribution of a dopant included in the second epitaxial layer in a surface parallel with the surface of the substrate main body.

摘要翻译： 为了抑制电荷平衡的劣化，并且在半导体衬底上形成超结结构之后保持优异的耐电压特性，多个柱状第一外延层分别以预定间隔分别形成在衬底主体的表面上，并且多个 的第二外延层分别形成在多个第一外延层之间的沟槽中。 在与基板主体的表面平行的表面中包含在第一外延层中的掺杂剂的浓度分布被配置为与包含在第二外延层中的掺杂剂的浓度分布在与 基板主体。

公开(公告)号：USRE44236E1

公开(公告)日：2013-05-21

申请号：US13271485

申请日：2011-10-12

申请人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Tomoatsu Makino ,  Syouji Nogami ,  Tomonori Yamaoka

发明人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Tomoatsu Makino ,  Syouji Nogami ,  Tomonori Yamaoka

IPC分类号： H01L21/20

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L29/0634 ,  H01L29/7811

摘要： A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.

公开(公告)号：US07633123B2

公开(公告)日：2009-12-15

申请号：US11645792

申请日：2006-12-27

申请人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Yoshiyuki Hattori ,  Kyoko Okada

发明人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Yoshiyuki Hattori ,  Kyoko Okada

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36

摘要： A semiconductor device includes: two main electrodes; multiple first regions; and multiple second regions. The first region having a first impurity concentration and a first width and the second region having a second impurity concentration and a second width are alternately repeated. A product of the first impurity concentration and the first width is equal to a product of the second impurity concentration and the second width. The first width is equal to or smaller than 4.5 μm. The first impurity concentration is lower than a predetermined concentration satisfying a RESURF condition. A ratio between on-state resistances of the device at 27° C. and at 150° C. is smaller than 1.8.

摘要翻译： 半导体器件包括：两个主电极; 多个第一区域; 和多个第二区域。 交替重复具有第一杂质浓度和第一宽度的第一区域和具有第二杂质浓度和第二宽度的第二区域。 第一杂质浓度和第一宽度的乘积等于第二杂质浓度与第二宽度的乘积。 第一宽度等于或小于4.5μm。 第一杂质浓度低于满足RESURF条件的预定浓度。 器件在27°C和150°C的导通电阻之间的比值小于1.8。

公开(公告)号：US20070032092A1

公开(公告)日：2007-02-08

申请号：US11496708

申请日：2006-08-01

申请人： Takumi Shibata ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Masaru Hori

发明人： Takumi Shibata ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Masaru Hori

IPC分类号： H01L21/311 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28525 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28562 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/66734

摘要： A method for manufacturing a semiconductor device includes steps of: forming a trench on a semiconductor substrate, which is made of silicon; and filling the trench with an epitaxial layer. The epitaxial layer is made of silicon, and the step of filling the trench includes a step of performing a plasma CVD method with using a silicon source gas. By using anisotropic character of a plasma, the epitaxial layer is selectively deposited on a bottom of the trench. Thus, the trench is filled with the epitaxial layer having no void.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在由硅制成的半导体衬底上形成沟槽; 并用外延层填充沟槽。 外延层由硅制成，填充沟槽的步骤包括使用硅源气体进行等离子体CVD法的步骤。 通过使用等离子体的各向异性特征，外延层选择性地沉积在沟槽的底部。 因此，沟槽被无空隙的外延层填充。

公开(公告)号：US07063751B2

公开(公告)日：2006-06-20

申请号：US10132298

申请日：2002-04-26

申请人： Yasushi Urakami ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

发明人： Yasushi Urakami ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

IPC分类号： H01L29/12 ,  H01L29/30 ,  H01L21/20 ,  H01L21/36 ,  H01L29/04

CPC分类号： H01L21/763 ,  H01L21/30608 ,  H01L21/761

摘要： A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that the width of the mask opening width is greater than the width of the trench. After that, the inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished to complete the substrate.

摘要翻译： 通过由形成在半导体衬底上的氧化硅膜构成的掩模，在半导体衬底中形成沟槽。 然后，蚀刻掩模的开口部分的边缘部分，使得掩模开口宽度的宽度大于沟槽的宽度。 之后，通过在低压下在非氧化或非氮化气氛中在1000℃左右的热处理使沟槽的内表面平滑化。 然后，沟槽填充有外延膜。 之后，抛光外延膜以完成基板。

公开(公告)号：US06836001B2

公开(公告)日：2004-12-28

申请号：US10442196

申请日：2003-05-21

申请人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Jun Sakakibara ,  Nobuhiro Tsuji

发明人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Jun Sakakibara ,  Nobuhiro Tsuji

IPC分类号： H01L2904

CPC分类号： H01L29/781 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/7813

摘要： A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.

摘要翻译： 半导体器件包括半导体衬底和半导体层。 半导体衬底具有作为Si {100}表面的主表面。 基板在主表面具有沟槽。 半导体层位于限定沟槽的表面上，以与半导体衬底具有共同的结晶平面。 沟槽由底面，彼此面对的两个长侧壁表面和彼此相对的两个短侧壁表面限定。 底表面和长侧壁表面是Si {100}表面。

公开(公告)号：US06406982B2

公开(公告)日：2002-06-18

申请号：US09870705

申请日：2001-06-01

申请人： Yasushi Urakami ,  Shoichi Yamauchi ,  Toshio Sakakibara ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

发明人： Yasushi Urakami ,  Shoichi Yamauchi ,  Toshio Sakakibara ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

IPC分类号： H01L2120

CPC分类号： H01L21/763 ,  H01L21/30608 ,  H01L21/761

摘要： A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.

摘要翻译： 通过由形成在半导体衬底上的氧化硅膜构成的掩模，在半导体衬底中形成沟槽。 然后，蚀刻掩模的开口部分的边缘部分，使得其开口宽度比沟槽的宽度宽。 之后，通过在低压下在非氧化或非氮化气氛中在1000℃左右的热处理使沟槽的内表面平滑化。 然后，沟槽填充有外延膜。 之后，对该外延膜进行研磨，得到半导体装置的半导体基板。

公开(公告)号：US07517771B2

公开(公告)日：2009-04-14

申请号：US11496708

申请日：2006-08-01

申请人： Takumi Shibata ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Masaru Hori

发明人： Takumi Shibata ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Masaru Hori

IPC分类号： H01L21/76

CPC分类号： H01L21/28525 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28562 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/66734

摘要： A method for manufacturing a semiconductor device includes steps of: forming a trench on a semiconductor substrate, which is made of silicon; and filling the trench with an epitaxial layer. The epitaxial layer is made of silicon, and the step of filling the trench includes a step of performing a plasma CVD method with using a silicon source gas. By using anisotropic character of a plasma, the epitaxial layer is selectively deposited on a bottom of the trench. Thus, the trench is filled with the epitaxial layer having no void.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在由硅制成的半导体衬底上形成沟槽; 并用外延层填充沟槽。 外延层由硅制成，填充沟槽的步骤包括使用硅源气体进行等离子体CVD法的步骤。 通过使用等离子体的各向异性特征，外延层选择性地沉积在沟槽的底部。 因此，沟槽被无空隙的外延层填充。