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    Method for shallow trench isolations with chemical-mechanical polishing
    1.
    发明授权
    Method for shallow trench isolations with chemical-mechanical polishing 失效
    化学机械抛光浅沟槽隔离方法

    公开(公告)号：US6060370A

    公开(公告)日：2000-05-09

    申请号：US98635

    申请日：1998-06-16

    申请人： Shouli Steve Hsia ,  Yanhua Wang ,  Jayanthi Pallinti

    发明人： Shouli Steve Hsia ,  Yanhua Wang ,  Jayanthi Pallinti

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76229

    摘要： A process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate is described. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material. A yet another step of the process includes polishing the integrated circuit substrate surface to remove a substantial portion of the composite layered stack and a portion of the insulating material adjacent to the composite layered stack at about a same rate. The polishing step facilitates in forming a substantially planar surface of the insulating material above the trench and reducing a likelihood of forming of a concave region near a middle region of the surface of the insulating material. The concave region recesses inwardly into the surface of the insulating material in the trench.

    摘要翻译： 描述了在集成电路基板的表面中制造填充有绝缘材料的沟槽的工艺。 该方法的一个步骤包括在集成电路基板表面上待保护的区域上的复合分层堆叠上限定掩模层。 复合层叠堆叠包括第一材料层和抛光停止层。 第一材料的层通过化学机械抛光具有比通过绝缘材料的化学机械抛光的抛光速率大的抛光速率。 该方法的另一步骤包括通过复合层叠堆叠和集成电路衬底进行蚀刻以在集成电路衬底表面中形成沟槽，并将绝缘材料沉积在集成电路衬底表面上，使得沟槽填充有绝缘材料。 该方法的另一步骤包括抛光集成电路衬底表面以大致相同的速率去除复合层叠堆叠的大部分和与复合层叠堆叠相邻的绝缘材料的一部分。 抛光步骤有助于在沟槽上方形成绝缘材料的基本平坦的表面，并减少在绝缘材料的表面的中间区域附近形成凹陷区域的可能性。 凹入区域向内凹入沟槽中绝缘材料的表面。

    Shallow trench isolation chemical-mechanical polishing process
    2.
    发明授权
    Shallow trench isolation chemical-mechanical polishing process 有权
    浅沟隔离化学机械抛光工艺

    公开(公告)号：US06424019B1

    公开(公告)日：2002-07-23

    申请号：US09507042

    申请日：2000-02-18

    申请人： Shouli Steve Hsia ,  Yanhua Wang ,  Jayanthi Pallinti

    发明人： Shouli Steve Hsia ,  Yanhua Wang ,  Jayanthi Pallinti

    IPC分类号： H01C2900

    CPC分类号： H01L21/76229

    摘要： A process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate is described. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material. A yet another step of the process includes polishing the integrated circuit substrate surface to remove a substantial portion of the composite layered stack and a portion of the insulating material adjacent to the composite layered stack at about a same rate. The polishing step facilitates in forming a substantially planar surface of the insulating material above the trench and reducing a likelihood of forming of a concave region near a middle region of the surface of the insulating material. The concave region recesses inwardly into the surface of the insulating material in the trench.

    摘要翻译： 描述了在集成电路基板的表面中制造填充有绝缘材料的沟槽的工艺。 该方法的一个步骤包括在集成电路基板表面上待保护的区域上的复合分层堆叠上限定掩模层。 复合层叠堆叠包括第一材料层和抛光停止层。 第一材料的层通过化学机械抛光具有比通过绝缘材料的化学机械抛光的抛光速率大的抛光速率。 该方法的另一步骤包括通过复合层叠堆叠和集成电路衬底进行蚀刻以在集成电路衬底表面中形成沟槽，并将绝缘材料沉积在集成电路衬底表面上，使得沟槽填充有绝缘材料。 该方法的另一步骤包括抛光集成电路衬底表面以大致相同的速率去除复合层叠堆叠的大部分和与复合层叠堆叠相邻的绝缘材料的一部分。 抛光步骤有助于在沟槽上方形成绝缘材料的基本平坦的表面，并减少在绝缘材料的表面的中间区域附近形成凹陷区域的可能性。 凹入区域向内凹入沟槽中绝缘材料的表面。

    Metal interconnect stack for integrated circuit structure
    3.
    发明授权
    Metal interconnect stack for integrated circuit structure 有权
    金属互连堆栈用于集成电路结构

    公开(公告)号：US06087726A

    公开(公告)日：2000-07-11

    申请号：US261270

    申请日：1999-03-01

    申请人： Shouli Steve Hsia ,  Zhihai Wang ,  Fred Chen

    发明人： Shouli Steve Hsia ,  Zhihai Wang ,  Fred Chen

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76871 ,  H01L21/76841 ,  H01L23/53223 ,  H01L2221/1089 ,  H01L2924/0002

    摘要： A metal interconnect stack for an integrated circuit structure is described comprising a main metal interconnect layer, an underlying TiN barrier layer and a titanium metal seed layer below the TiN barrier layer, and a barrier layer below the titanium metal seed layer to provide protection against chemical interaction between the titanium metal seed layer and an underlying plug in a via. The structure is formed by providing an integrated circuit structure having an insulation layer formed thereon with one or more metal-filled vias or contact openings generally vertically formed therethrough to have an upper surface thereon; forming a lower barrier layer such as a TiN barrier layer over the insulation layer and the upper surface of the metal in the one or more metal-filled vias; and subsequently forming the titanium seed layer over the lower TiN barrier layer. This new first TiN barrier layer then separates the surface of the metal in the one or more vias from the titanium seed layer in the metal interconnect stack to inhibit galvanic action between the metal in the one or more vias and the titanium seed layer. Preferably, the main metal interconnect layer is provided with a crystallographic orientation to enhance the electron migration of the main metal interconnect layer. To achieve this orientation in the main metal interconnect layer, the main titanium nitride barrier layer is preferably also provided with crystallographic orientation and the titanium metal seed layer functions as a seed layer for the second TiN barrier layer which will, in turn, act as a seed layer for the main metal interconnect layer. An optional third TiN barrier layer may be formed over the main metal interconnect layer.

    摘要翻译： 描述了一种用于集成电路结构的金属互连堆叠，其包括主金属互连层，下面的TiN阻挡层和TiN阻挡层下面的钛金属种子层，以及在钛金属种子层下面的阻挡层以提供防止化学 钛金属种子层与通孔中的下面的塞子之间的相互作用。 该结构通过提供一种集成电路结构形成，该集成电路结构具有在其上形成有一个或多个金属填充的通孔或通过其垂直形成的接触开口的绝缘层，以在其上具有上表面; 在一个或多个金属填充的通孔中在绝缘层和金属的上表面上形成诸如TiN阻挡层的下阻挡层; 随后在下部TiN阻挡层上形成钛籽晶层。 然后，该新的第一TiN阻挡层将金属互连叠层中的一个或多个通孔中的金属表面与钛籽晶层分离，以抑制一个或多个通孔中的金属与钛籽晶层之间的电流作用。 优选地，主金属互连层具有<111>晶体取向以增强主金属互连层的电子迁移。 为了在主金属互连层中实现这种<111>取向，主要的氮化钛阻挡层优选还具有<111>晶体取向，并且钛金属种子层用作第二TiN阻挡层的种子层， 又作为主金属互连层的籽晶层。 可以在主金属互连层上形成可选的第三TiN阻挡层。

    Process for forming metal interconnect stack for integrated circuit structure
    4.
    发明授权
    Process for forming metal interconnect stack for integrated circuit structure 有权
    用于形成用于集成电路结构的金属互连叠层的工艺

    公开(公告)号：US06174798B1

    公开(公告)日：2001-01-16

    申请号：US09427572

    申请日：1999-10-26

    申请人： Shouli Steve Hsia ,  Zhihai Wang ,  Fred Chen

    发明人： Shouli Steve Hsia ,  Zhihai Wang ,  Fred Chen

    IPC分类号： H01L214763

    CPC分类号： H01L21/76871 ,  H01L21/76841 ,  H01L23/53223 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making a metal interconnect stack for an integrated circuit structure is described comprising a main metal interconnect layer, an underlying TiN barrier layer and a titanium metal seed layer below the TiN barrier layer, and a barrier layer below the titanium metal seed layer to provide protection against chemical interaction between the titanium metal seed layer and an underlying plug in a via. The structure is formed by providing an integrated circuit structure having an insulation layer formed thereon with one or more metal-filled vias or contact openings generally vertically formed therethrough to have an upper surface thereon; forming a lower barrier layer such as a TiN barrier layer over the insulation layer and the upper surface of the metal in the one or more metal-filled vias; and subsequently forming the titanium seed layer over the lower TiN barrier layer. This new first TiN barrier layer then separates the surface of the metal in the one or more vias from the titanium seed layer in the metal interconnect stack to inhibit galvanic action between the metal in the one or more vias and the titanium seed layer. Preferably, the main metal interconnect layer is provided with a crystallographic orientation to enhance the electron migration of the main metal interconnect layer. To achieve this orientation in the main metal interconnect layer, the main titanium nitride barrier layer is preferably also provided with crystallographic orientation and the titanium metal seed layer functions as a seed layer for the second TiN barrier layer which will, in turn, act as a seed layer for the main metal interconnect layer. An optional third TiN barrier layer may be formed over the main metal interconnect layer.

    摘要翻译： 描述了制造用于集成电路结构的金属互连堆叠的方法，其包括主金属互连层，下面的TiN阻挡层和在TiN阻挡层下面的钛金属种子层，以及在钛金属种子层下面的阻挡层， 提供防止钛金属种子层和通孔中的下面的插塞之间的化学相互作用的保护。 该结构通过提供一种集成电路结构形成，该集成电路结构具有在其上形成有一个或多个金属填充的通孔或通过其垂直形成的接触开口的绝缘层，以在其上具有上表面; 在一个或多个金属填充的通孔中在绝缘层和金属的上表面上形成诸如TiN阻挡层的下阻挡层; 随后在下部TiN阻挡层上形成钛籽晶层。 然后，该新的第一TiN阻挡层将金属互连叠层中的一个或多个通孔中的金属表面与钛籽晶层分离，以抑制一个或多个通孔中的金属与钛籽晶层之间的电流作用。 优选地，主金属互连层具有<111>晶体取向以增强主金属互连层的电子迁移。 为了在主金属互连层中实现这种<111>取向，主要的氮化钛阻挡层优选还具有<111>晶体取向，并且钛金属种子层用作第二TiN阻挡层的种子层， 又作为主金属互连层的籽晶层。 可以在主金属互连层上形成可选的第三TiN阻挡层。

    Modified multilayered metal line structure for use with tungsten-filled vias in integrated circuit structures
    6.
    发明授权
    Modified multilayered metal line structure for use with tungsten-filled vias in integrated circuit structures 失效
    用于集成电路结构中的钨填充通孔的改进的多层金属线结构

    公开(公告)号：US6147409A

    公开(公告)日：2000-11-14

    申请号：US98019

    申请日：1998-06-15

    申请人： Shouli Steve Hsia ,  Fred Chen ,  Jiunn-Yann Tsai

    发明人： Shouli Steve Hsia ,  Fred Chen ,  Jiunn-Yann Tsai

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/53223 ,  H01L2924/0002

    摘要： A composite metal line structure for an integrated circuit structure on a semiconductor substrate is disclosed which comprises: a low resistance metal core layer; a first thin protective layer of electrically conductive material on the upper surface of the metal core layer capable of protecting the metal core layer from reaction with tungsten; a layer of tungsten formed over the first protective layer to function as an etch stop layer for vias subsequently formed in an overlying dielectric layer; and a second thin protective layer of electrically conductive material over the tungsten layer and capable of functioning as an antireflective coating (ARC). When a dielectric layer is formed over the composite metal line structure, tungsten-filled vias can be formed in the dielectric layer which will extend down through the second thin protective layer to provide direct electrical contact between the tungsten-filled via and the tungsten layer of the composite metal line structure, thereby providing a low resistance contact between the tungsten-filled via and the composite metal line structure.

    摘要翻译： 公开了一种用于半导体衬底上的集成电路结构的复合金属线结构，其包括：低电阻金属芯层; 金属芯层的上表面上的第一薄导电材料保护层，其能够保护金属芯层免受钨的反应; 形成在第一保护层上的钨层，用作随后在上覆介电层中形成的通孔的蚀刻停止层; 以及在钨层上方的能够用作抗反射涂层（ARC）的导电材料的第二薄保护层。 当在复合金属线结构上形成电介质层时，可以在电介质层中形成钨填充的通孔，该介电层将向下延伸穿过第二薄保护层，以在填充钨的通孔和钨层之间提供直接的电接触 复合金属线结构，从而在填充钨的通孔和复合金属线结构之间提供低电阻接触。

    Process for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structure
    7.
    发明授权
    Process for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structure 失效
    用于在集成电路结构的多个介电层中形成通孔和金属线的沟槽的工艺

    公开(公告)号：US6037262A

    公开(公告)日：2000-03-14

    申请号：US98032

    申请日：1998-06-15

    申请人： Shouli Steve Hsia ,  Jiunn-Yann Tsai

    发明人： Shouli Steve Hsia ,  Jiunn-Yann Tsai

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/311

    CPC分类号： H01L21/76808 ,  H01L23/5226 ,  H01L2221/1031 ,  H01L2924/0002

    摘要： A process is disclosed for forming vias and trenches in two separate dielectric layers, which may be separated by an etch stop, while avoiding the etch mask stress complicated resist masks, or high aspect ratio openings of the prior art. A first dielectric layer 10 is formed over an integrated circuit structure 2 on a semiconductor substrate, and a thin second dielectric layer 20 is formed over the first dielectric layer. A first resist mask, is formed over the second dielectric layer, and the first and second dielectric layers are etched through to form one or more vias 18, 28 extending through both the first and second dielectric layers. The first resist mask is then removed and a third dielectric layer 70, having different etch characteristics than the second dielectric layer, is deposited over the structure. This third dielectric layer, which may comprise the same material as the first dielectric layer, is applied to the structure as a low step coverage, nonconformal coating layer which preferably does not completely fill the one or more vias already formed in the first and second dielectric layers. A second resist mask is then applied over the third dielectric layer and the third dielectric layer is etched through to the underlying second dielectric layer to form the desired trench openings 78, with the second dielectric material acting as an etch stop, and also as an etch mask for removal of any of the third dielectric layer material which has deposited in the via(s) previously formed in the first and second dielectric layers.

    摘要翻译： 公开了一种用于在两个单独的电介质层中形成通路和沟槽的工艺，其可通过蚀刻停止层分开，同时避免了现有技术的蚀刻掩模应力复杂的抗蚀剂掩模或高纵横比开口。 第一电介质层10形成在半导体衬底上的集成电路结构2上，并且在第一介电层上形成薄的第二电介质层20。 第一抗蚀剂掩模形成在第二介电层上，并且第一和第二介电层被蚀刻通过以形成延伸穿过第一和第二介电层的一个或多个通孔18,28。 然后去除第一抗蚀剂掩模，并且在结构上沉积具有不同于第二介电层的蚀刻特性的第三介电层70。 该第三电介质层可以包括与第一电介质层相同的材料作为低阶覆盖，非共形涂层，优选地不完全填充已经形成在第一和第二电介质中的一个或多个通孔 层。 然后将第二抗蚀剂掩模施加在第三介电层上，并且第三电介质层被蚀刻到下面的第二介电层上以形成所需的沟槽开口78，第二介电材料用作蚀刻停止层，并且还作为蚀刻 掩模，用于去除沉积在先前形成在第一和第二电介质层中的通孔中的任何第三电介质层材料。