公开(公告)号：US07571258B2

公开(公告)日：2009-08-04

申请号：US10718270

申请日：2003-11-19

申请人： Shridhar Mukund ,  Anjan Mitra ,  Mahesh Gopalan

发明人： Shridhar Mukund ,  Anjan Mitra ,  Mahesh Gopalan

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04J3/16 ,  H04J3/22 ,  G06F15/16

CPC分类号： H04L49/3063 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161

摘要： A method for efficiently processing layers of a data packet is provided. The method initiates with defining a pipeline of processors communicating with a distributed network and CPU of a host system. Then, a data packet from the distributed network is received into a first stage of the pipeline. Next, the data packet is processed to remove a header associated with the first stage. Then, the processed data packet is transmitted to a second stage. The operations of processing and transmitting the processed data packet are repeated for successive stages until a header associated with a final stage has been removed. Then, the data packet is transmitted to the CPU of the host system. It should be appreciated that the header is not necessarily transformed at each stage. For example, suitable processing that does not strip the header may be applied at each stage.

摘要翻译： 提供了一种用于有效处理数据分组的层的方法。 该方法通过定义与主机系统的分布式网络和CPU通信的处理器流水线来启动。 然后，来自分布式网络的数据分组被接收到流水线的第一级。 接下来，处理数据分组以移除与第一阶段相关联的报头。 然后，处理的数据分组被发送到第二阶段。 处理和发送处理的数据分组的操作重复连续阶段，直到与最后一级相关联的报头已经被去除。 然后，将数据包发送到主机系统的CPU。 应当理解，头部不一定在每个阶段变换。 例如，可以在每个阶段应用不剥离报头的适当处理。

公开(公告)号：US07849441B2

公开(公告)日：2010-12-07

申请号：US11426882

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

发明人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

IPC分类号： G06F9/44

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

摘要翻译： 提供了一种用于指定有状态的，面向事务的系统的方法。 该方法通过指定多个原始FlowModules来启动。 该方法包括在多个FlowModules中的每一个中定义至少一个FlowGate，其中每个FlowGate包括不可中断的过程代码序列，单个入口点，并由命名的并发调用进行调用。 从调用FlowGate指定一个Arc到被称为FlowGate的Arc，并且为被调用的FlowGate的每个命名调用生成一个Signal。 定义一个通道用于携带信号。 提供了用于在半导体器件中合成半导体器件和路由信号的方法。

公开(公告)号：US20060294483A1

公开(公告)日：2006-12-28

申请号：US11426880

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

摘要翻译： 提供半导体存储器件。 半导体存储器件包括布置在多个列组中的多个存储器单元，每个列组具有用于独立多路可配置存取的多个列和多个外部位线。 列组在外部位线中具有第一，第二和第三层级。 层级的第一级提供与多个存储器单元的连接。 层级的第二级提供了用于将数据从列组中的每个列复用到中间位线的第一拼接器。 该层级的第三级包括用于将数据复用到从多个外部访问路径到中间位线的数据的第二拼接器。 还提供了一种结构可重构电路装置和用于设计电路的方法。

公开(公告)号：US06901496B1

公开(公告)日：2005-05-31

申请号：US10264580

申请日：2002-10-04

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： H04L29/06 ,  G06F12/00

CPC分类号： H04L69/12

摘要： A network interface card is provided. The network interface card includes a plurality of pipelined processors. Each of the pipelined processors includes an input socket having at least three single ported memory regions configured to store variable-size data packets. The at least three single ported memory regions enable a downstream processor reading the variable-size data packets from the single ported memory regions to maintain a data throughput to support an incoming line rate of a data stream. The line rate data throughput is maintained after a maximum size data packet has been read by the downstream processor. Methods of method for optimizing throughput between a producing processor and a consuming processor and a processor are also provided.

摘要翻译： 提供网络接口卡。 网络接口卡包括多个流水线处理器。 每个流水线处理器包括具有至少三个单端口存储区域的输入套接字，其被配置为存储可变大小的数据分组。 所述至少三个单端口存储器区域使得下游处理器能够从单个端口存储器区域读取可变大小的数据分组，以维持数据吞吐量以支持数据流的输入线路速率。 在下游处理器读取最大尺寸数据包之后，维持线路速率数据吞吐量。 还提供了用于优化生产处理器和消费处理器和处理器之间的吞吐量的方法的方法。

公开(公告)号：US20100008155A1

公开(公告)日：2010-01-14

申请号：US12561460

申请日：2009-09-17

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： G11C7/10 ,  G06F17/50 ,  H03K19/003 ,  H03K19/173

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

摘要翻译： 提供半导体存储器件。 半导体存储器件包括布置在多个列组中的多个存储器单元，每个列组具有用于独立多路可配置存取的多个列和多个外部位线。 列组在外部位线中具有第一，第二和第三层级。 层级的第一级提供与多个存储器单元的连接。 层级的第二级提供了用于将数据从列组中的每个列复用到中间位线的第一拼接器。 该层级的第三级包括用于将数据复用到从多个外部访问路径到中间位线的数据的第二拼接器。 还提供了一种结构可重构电路装置和用于设计电路的方法。

公开(公告)号：US07614020B2

公开(公告)日：2009-11-03

申请号：US11426880

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

摘要翻译： 提供半导体存储器件。 半导体存储器件包括布置在多个列组中的多个存储器单元，每个列组具有用于独立多路可配置存取的多个列和多个外部位线。 列组在外部位线中具有第一，第二和第三层级。 层级的第一级提供与多个存储器单元的连接。 层级的第二级提供了用于将数据从列组中的每个列复用到中间位线的第一拼接器。 该层级的第三级包括用于将数据复用到从多个外部访问路径到中间位线的数据的第二拼接器。 还提供了一种结构可重构电路装置和用于设计电路的方法。

公开(公告)号：US20070150854A1

公开(公告)日：2007-06-28

申请号：US11426882

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

发明人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

IPC分类号： G06F9/44

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

摘要翻译： 提供了一种用于指定有状态的，面向事务的系统的方法。 该方法通过指定多个原始FlowModules来启动。 该方法包括在多个FlowModules的每一个内定义至少一个FlowGate，其中每个FlowGate包括不可中断的过程代码序列，单个入口点，并由命名的并发调用进行调用。 从调用FlowGate指定一个Arc到被称为FlowGate的Arc，并且为被调用的FlowGate的每个命名调用生成一个Signal。 定义一个通道用于携带信号。 提供了用于在半导体器件中合成半导体器件和路由信号的方法。

公开(公告)号：US06961893B1

公开(公告)日：2005-11-01

申请号：US10113147

申请日：2002-03-28

申请人： Shridhar Mukund ,  Manish Mahajan ,  Vasantha Srirambhatla ,  T.V.P. Kameswar Rao ,  Anjan Mitra

发明人： Shridhar Mukund ,  Manish Mahajan ,  Vasantha Srirambhatla ,  T.V.P. Kameswar Rao ,  Anjan Mitra

IPC分类号： H03M13/09 ,  H03M13/11 ,  H04L1/00 ,  H04L29/06 ,  H03M13/00

CPC分类号： H03M13/091

摘要： A method and apparatus for performing a cyclic redundancy check (CRC) process is provided. The CRC is capable of being performed on data received out of order without having to store and assemble the data. One exemplary method for computing a CRC for a transmitted data stream initiates with performing a CRC process on a first segment of the data stream to generate a first CRC remainder. Next, the first CRC remainder for the first segment is projected. Then, the CRC process on a second segment of the data stream is performed to generate a second CRC remainder. Next, the second CRC remainder for the second segment is projected. Then, the projected remainders are combined to calculate a complete CRC remainder for the data stream in an order independent fashion. Data streams including multiple segments can be handled by the CRC process.

摘要翻译： 提供了一种用于执行循环冗余校验（CRC）处理的方法和装置。 CRC能够对不依次接收的数据执行，而不必存储和组合数据。 用于计算发送数据流的CRC的一个示例性方法通过在数据流的第一段上执行CRC处理来产生第一CRC余数。 接下来，投影第一段的第一个CRC余数。 然后，执行数据流的第二段上的CRC处理以产生第二CRC余数。 接下来，投影第二段的第二CRC余数。 然后，将投影的余数组合起来，以独立的顺序为数据流计算完整的CRC余数。 包括多个段的数据流可以由CRC处理来处理。

公开(公告)号：US20110035722A1

公开(公告)日：2011-02-10

申请号：US12906967

申请日：2010-10-18

申请人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

发明人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

IPC分类号： G06F9/44

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

摘要翻译： 提供了一种用于指定有状态的，面向事务的系统的方法。 该方法通过指定多个原始FlowModules来启动。 该方法包括在多个FlowModules中的每一个中定义至少一个FlowGate，其中每个FlowGate包括不可中断的过程代码序列，单个入口点，并由命名的并发调用进行调用。 从调用FlowGate指定一个Arc到被称为FlowGate的Arc，并且为被调用的FlowGate的每个命名调用生成一个Signal。 定义一个通道用于携带信号。 提供了用于在半导体器件中合成半导体器件和路由信号的方法。

公开(公告)号：US07676783B2

公开(公告)日：2010-03-09

申请号：US11426887

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： An apparatus for performing in-memory computation for stateful, transaction-oriented applications is provided. The apparatus includes a multi-level array of storage cells. The storage cells are configurable for a read access from one of a plurality of access data paths. The plurality of access data paths are also configurable for a write access from one of the plurality of access data paths. The multi-level array is capable of being configurable into logical partitions with arbitrary starting addresses. The apparatus further includes a compute element in communication with the multi-level array over the plurality of access data paths, the compute element configured to issue a plurality of memory accesses to the multi-level array through the plurality of access data paths. Methods for programming a multi-level array of storage cells and for processor design are also provided.

摘要翻译： 提供了一种用于对有状态的面向事务的应用执行内存中计算的设备。 该装置包括存储单元的多级阵列。 存储单元可配置用于从多个访问数据路径之一进行读访问。 多个访问数据路径也可配置用于从多个访问数据路径中的一个访问数据路径进行写访问。 多级阵列能够被配置成具有任意起始地址的逻辑分区。 所述设备还包括与所述多个访问数据路径上的所述多级阵列通信的计算元件，所述计算元件被配置为通过所述多个访问数据路径发布对所述多级阵列的多个存储器访问。 还提供了用于编程存储单元的多级阵列和处理器设计的方法。