公开(公告)号：US20050091478A1

公开(公告)日：2005-04-28

申请号：US10617506

申请日：2003-07-11

申请人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

发明人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/45 ,  G06F9/00

CPC分类号： G06F9/30058 ,  G06F8/447 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3842

摘要： A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.

摘要翻译： 解码并执行指令序列的处理器包括：状态保持单元，用于当执行预定指令时，保持所述预定指令的执行结果的更新状态; 获取单元，用于获得指令序列，所述指令序列由与分配给所述处理器的指令集的指令相匹配的指令组合，其中所述指令集被分配了第一条件指令;第一条件指令的第一状态条件与第二状态条件相互排斥， 第二条件指令，其具有与第一条件指令相同的操作码，指令集不被分配第二条件指令，以及指定一个状态和多个状态中的一个状态和多个状态的第一状态条件和第二状态条件; 解码单元，用于逐个地解码所获得的指令序列中的每个指令; 判断单元，用于当解码单元解码第一条件指令时，判断更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态; 以及执行单元，用于仅当判断单元的判断结果为肯定时，执行由解码单元解码的第一条件指令中由操作码指定的操作。

公开(公告)号：US06230258B1

公开(公告)日：2001-05-08

申请号：US09144298

申请日：1998-08-31

申请人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

发明人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

IPC分类号： G06F930

CPC分类号： G06F9/30058 ,  G06F8/447 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3842

摘要： An instruction conversion apparatus and method for converting instruction sequences not including conditional instructions into instruction sequences including conditional instructions wherein the conditional instructions include both a condition and an operation code for execution by the processor when the condition is satisfied. An obtaining unit receives an instruction sequence that does not include a conditional instruction whereby an instruction sequence detection unit detects a conversion target instruction sequence which transfers different transfer objects to the same storage resource when a predetermined condition is satisfied. A judging unit judges whether the instruction set of a specialized processor is assigned a conditional instruction including the same condition as the precondition whereby a conversion unit can then convert the conversion target instruction sequence into the instruction sequence including a conditional instruction with the predetermined condition. While the judgment unit decision is negative, the conversion unit converts the conversion target instruction sequence into an instruction sequence including a conditional instruction with a condition that is mutually exclusive with the predetemiined condition.

摘要翻译： 一种用于将不包括条件指令的指令序列转换成包括条件指令的指令序列的指令转换装置和方法，其中条件指令包括当条件满足时由处理器执行的条件和操作代码两者。 获取单元接收不包括条件指令的指令序列，由此当满足预定条件时，指令序列检测单元检测到将不同转移对象传送到同一存储资源的转换目标指令序列。 判断单元判断专用处理器的指令集是否被分配条件指令，该条件指令包括与前提条件相同的条件，由此转换单元然后可以将转换目标指令序列转换为包括具有预定条件的条件指令的指令序列。 当判断单元判定为否定时，转换单元将转换目标指令序列转换成具有条件的条件指令的指令序列，该条件与预先设定的条件相互排斥。

公开(公告)号：US06219779B1

公开(公告)日：2001-04-17

申请号：US09097214

申请日：1998-06-12

申请人： Shuichi Takayama ,  Nobuo Higaki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Masato Suzuki

发明人： Shuichi Takayama ,  Nobuo Higaki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Masato Suzuki

IPC分类号： G06F930

CPC分类号： G06F9/324 ,  G06F9/30101 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3885 ,  G06F9/461

摘要： A processor includes a constant register 36 for storing a constant, a format decoder 21 for decoding a format code located in the P0.0 field of an instruction stored in the instruction register 10, and a constant register control unit 32 which, when the format decoder 21 has decoded that the instruction includes a constant to be stored in the constant register 36, shifts the presently stored value in the constant register 36 and stores the constant into the constant register 36.

摘要翻译： 处理器包括用于存储常数的常数寄存器36，用于解码存储在指令寄存器10中的指令的P0.0字段中的格式代码的格式解码器21以及常数寄存器控制单元32，当格式 解码器21已经解码了指令包括要存储在常数寄存器36中的常数，将当前存储的值移位到常数寄存器36中，并将常数存储到常数寄存器36中。

公开(公告)号：US06606703B2

公开(公告)日：2003-08-12

申请号：US09756068

申请日：2001-01-08

申请人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

发明人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

IPC分类号： G06F1500

CPC分类号： G06F9/30058 ,  G06F8/447 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3842

摘要： Processor and instruction conversion apparatus, including a technique for reducing the number of types of instructions and processor hardware scale when conditional instructions are used. The processor includes a stare hold unit, an obtaining unit, a decoding unit, a judging unit, and an execution unit. The judging unit judges whether a state hold unit renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction when decoded by the decoding unit. When the judgment is affirmative, the execution unit executes an operation specified by the operation code in the first conditional instruction decoded by the decoding unit. The instruction set is assigned first conditional instructions with a first state condition which is mutually exclusive with a second state condition for an unassigned second conditional instruction, both having the same operation code.

摘要翻译： 处理器和指令转换装置，包括当使用条件指令时减少指令类型数量和处理器硬件比例的技术。 处理器包括凝视保持单元，获取单元，解码单元，判断单元和执行单元。 当由解码单元解码时，判断单元判断状态保持单元更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态。 当判断为肯定时，执行单元执行由解码单元解码的第一条件指令中由操作码指定的操作。 指令集被分配具有第一状态条件的第一条件指令，该第一状态条件与用于未分配的第二条件指令的第二状态条件相互排斥，所述第二状态条件具有相同的操作代码。

公开(公告)号：US06880150B1

公开(公告)日：2005-04-12

申请号：US09301284

申请日：1999-04-28

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/44

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当指令解码器409a〜409c解码分支指令时，分支指令中包含的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US07076638B2

公开(公告)日：2006-07-11

申请号：US10246482

申请日：2002-09-19

申请人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

发明人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

IPC分类号： G06F9/30

CPC分类号： G06F9/3853 ,  G06F9/30072 ,  G06F9/3822

摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

公开(公告)号：US20060031661A1

公开(公告)日：2006-02-09

申请号：US11245357

申请日：2005-10-07

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/40

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当指令解码器409a-409c解码分支指令时，包括在分支指令中的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US07761692B2

公开(公告)日：2010-07-20

申请号：US11452282

申请日：2006-06-14

申请人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

发明人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

IPC分类号： G06F9/38 ,  G06F9/45

CPC分类号： G06F9/3853 ,  G06F9/30072 ,  G06F9/3822

摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

摘要翻译： 为了克服有条件执行的指令如果不满足条件而被执行为无操作指令的问题，导致硬件的利用效率差并且降低了有效性能，则处理器解码大于 提供的计算单元的数量并且在执行阶段之前用指令发布控制部分判断其执行条件，条件为假的指令被无效，并且分配后续的有效指令，使得有效地使用计算单元（硬件）。 编译器执行调度，使得执行条件为真的指令数量不超过硬件的并行度的上限。 在每个周期上平行布置的指令数可能超过硬件的并行程度。

公开(公告)号：US20060242387A1

公开(公告)日：2006-10-26

申请号：US11452282

申请日：2006-06-14

申请人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

发明人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

IPC分类号： G06F9/44

CPC分类号： G06F9/3853 ,  G06F9/30072 ,  G06F9/3822

摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

公开(公告)号：US06976245B2

公开(公告)日：2005-12-13

申请号：US10012725

申请日：2001-10-22

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G09F9/44

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当分支指令由指令解码器409a〜409c解码时，分支指令中包含的PC相对值的高29位被发送到上PC计算器411，低3位被发送到下PC计算器 405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。