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公开(公告)号：US20130058173A1
公开(公告)日：2013-03-07
申请号：US13607306
申请日：2012-09-07
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G06F3/0635 , G06F13/4022
摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.
摘要翻译： 根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，存储第一和第二模式信息的模式信息存储单元，能够通过第一总线接口设置的第一和第二模式信息 电路，基于第一模式信息操作的第一存储器核心，第一存储器核心连接到第一总线接口电路并被提供有第一时钟信号，第二存储器内核，第二存储器核心被提供有第二存储器核心 时钟信号和选择电路，其基于预定的切换信息选择性地将第二存储器核心连接到第一或第二总线接口电路，其中当第二存储器核心连接到第二存储器核心时，第二存储器核心基于第二模式信息操作 第二总线接口电路。
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2.发明授权公开(公告)号：US09202541B2
公开(公告)日：2015-12-01
申请号：US13607306
申请日：2012-09-07
CPC分类号： G11C7/22 , G06F3/0635 , G06F13/4022
摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.
摘要翻译： 根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，存储第一和第二模式信息的模式信息存储单元，能够通过第一总线接口设置的第一和第二模式信息 电路，基于第一模式信息操作的第一存储器核心，第一存储器核心连接到第一总线接口电路并被提供有第一时钟信号，第二存储器内核，第二存储器核心被提供有第二存储器核心 时钟信号和选择电路，其基于预定的切换信息选择性地将第二存储器核心连接到第一或第二总线接口电路，其中当第二存储器核心连接到第二存储器核心时，第二存储器核心基于第二模式信息操作 第二总线接口电路。
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公开(公告)号：US20100034039A1
公开(公告)日：2010-02-11
申请号：US12458428
申请日：2009-07-13
申请人： Kenjyu Shimogawa , Hiroshi Furuta
发明人： Kenjyu Shimogawa , Hiroshi Furuta
IPC分类号： G11C7/00
CPC分类号： G11C7/1033 , G06F11/1044 , G11C7/08 , G11C11/4091
摘要： A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of 2 or more) number of groups. Among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation.
摘要翻译： 半导体集成电路具有耦合到相同字线的存储器单元数量K（K是2个或更多个的自然数），以及耦合到存储单元的多个读出放大器电路。 多个读出放大器电路分为N个（N个是2个以上的自然数）组。 在N个组中，在第一组读出放大器电路被激活并执行预定的读出操作之后，激活第二组读出放大器电路并执行预定的读出操作， 读出放大器电路的第N组顺序地被激活，以执行预定的读出操作。
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公开(公告)号：US08519774B2
公开(公告)日：2013-08-27
申请号：US13620803
申请日：2012-09-15
申请人： Kenjyu Shimogawa , Hiroshi Furuta
发明人： Kenjyu Shimogawa , Hiroshi Furuta
IPC分类号： H03K3/01
摘要： A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal.
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公开(公告)号：US08310297B2
公开(公告)日：2012-11-13
申请号：US12929753
申请日：2011-02-14
申请人： Kenjyu Shimogawa , Hiroshi Furuta
发明人： Kenjyu Shimogawa , Hiroshi Furuta
IPC分类号： H03K3/01
CPC分类号： H03K5/05 , H01L2924/0002 , H03K3/0375 , H03K3/356156 , H03K2005/00058 , H01L2924/00
摘要： Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.
摘要翻译： 公开了一种半导体器件，包括：模式控制电路，当待机控制信号处于激活状态时，基于来自定时器电路的定时器输出信号，生成改变功能电路部分的逻辑状态的MODE控制输出信号 以及输出控制电路，其接收所述功能电路部的输出信号，并控制所述输出信号的输出; 基于通过延迟电路延迟MODE控制输出信号而产生的延迟输出信号。 当功能电路部分通过MODE控制输出信号改变逻辑状态时，输出控制电路不将功能电路部分输出信号传送到输出，而是在功能电路部分变化之前保持并输出功能电路部分输出信号 逻辑状态由MODE控制输出信号。
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公开(公告)号：US07940577B2
公开(公告)日：2011-05-10
申请号：US11592978
申请日：2006-11-06
申请人： Kenjyu Shimogawa , Hiroshi Furuta
发明人： Kenjyu Shimogawa , Hiroshi Furuta
IPC分类号： G11C7/00
CPC分类号： G11C5/14
摘要： The semiconductor integrated circuit device includes a voltage control circuit that generates a control voltage for deactivating a field effect transistor by a gate voltage. The voltage control circuit controls a voltage so as to substantially minimize the leakage current which flows when the field effect transistor is inactive with respect to a device temperature.
摘要翻译： 半导体集成电路器件包括电压控制电路，其产生用于通过栅极电压去激活场效应晶体管的控制电压。 电压控制电路控制电压，以使得当场效应晶体管相对于器件温度无效时流过的漏电流基本上最小化。
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公开(公告)号：US07274616B2
公开(公告)日：2007-09-25
申请号：US11322425
申请日：2006-01-03
CPC分类号： G11C11/417 , G11C5/147
摘要： An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.
摘要翻译： 集成电路装置包括具有由格栅状布置的CMOSFET形成的多个存储单元的SRAM单元阵列。 SRAM单元阵列在1位序列中具有一对电源线和地线。 集成电路装置还包括检测器，检测每1位序列的锁存的发生并输出检测信号;以及功率控制器，其针对每个1位序列控制对电力线的电源电压。 功率控制器根据检测信号将按照1位序列提供给电力线的电压降低到锁定状态下降到预定值。
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公开(公告)号：US20060164905A1
公开(公告)日：2006-07-27
申请号：US11322425
申请日：2006-01-03
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.
摘要翻译： 集成电路装置包括具有由格栅状布置的CMOSFET形成的多个存储单元的SRAM单元阵列。 SRAM单元阵列在1位序列中具有一对电源线和地线。 集成电路装置还包括检测器，检测每1位序列的锁存的发生并输出检测信号;以及功率控制器，其针对每个1位序列控制对电力线的电源电压。 功率控制器根据检测信号将按照1位序列提供给电力线的电压降低到锁定状态下降到预定值。
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9.发明申请Design method for semiconductor circuit device, design method for semiconductor circuit, and semiconductor circuit device 审中-公开半导体电路器件的设计方法，半导体电路的设计方法和半导体电路器件公开(公告)号：US20050144576A1
公开(公告)日：2005-06-30
申请号：US11019634
申请日：2004-12-23
申请人： Hiroshi Furuta , Kenjyu Shimogawa
发明人： Hiroshi Furuta , Kenjyu Shimogawa
IPC分类号： G06F17/50 , H01L21/00 , H01L21/336 , H01L21/82
CPC分类号： G06F17/5036 , G06F17/5045
摘要： In one embodiment of the present invention, in a discrete MOSFET, the ZTC point is determined by combining the variation of the drain current induced by the variation of the threshold voltage in response to the temperature and the variation of the drain current induced by the variation of the mobility in response to the temperature. The chips configured with a number of circuits, however, include the circuits whose main operation regions of the MOSFETs are different. In CMOS circuits, the MOSFETs operate in the saturation region. On the other hand, in analog circuits, such as sense amplifiers or bandgap circuits, the MOSFETs operate in the linear region. In the design of the temperature dependence of the chip, the design is achieved by independently different models for respective MOSFETs whose operation regions are different.
摘要翻译： 在本发明的一个实施例中，在分立MOSFET中，通过组合由阈值电压的变化引起的漏极电流的变化响应于温度和由变化引起的漏极电流的变化来确定ZTC点 的温度响应的流动性。 然而，配置有多个电路的芯片包括MOSFET的主要操作区域不同的电路。 在CMOS电路中，MOSFET在饱和区域工作。 另一方面，在诸如读出放大器或带隙电路的模拟电路中，MOSFET在线性区域中工作。 在设计芯片的温度依赖性时，设计是通过独立不同的型号实现的，其各自的MOSFET的工作区域不同。
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10.发明授权Semiconductor memory device having signal receiving facility fabricated from bi-CMOS circuits 失效具有由BI-CMOS电路组成的信号接收设备的半导体存储器件
公开(公告)号：US5202823A
公开(公告)日：1993-04-13
申请号：US673998
申请日：1991-03-25
申请人： Kenjyu Shimogawa
发明人： Kenjyu Shimogawa
IPC分类号： G11C5/14 , G11C11/415 , G11C11/418
CPC分类号： G11C11/418 , G11C5/143
摘要： A semiconductor memory device is fabricated from Bi-CMOS circuits and comprises a plurality of memory cells arranged in rows and columns, a plurality of word lines respectively coupled to the rows of the plurality of memory cells, a row address buffer unit coupled between first and second power voltage sources and supplied with row address bits for producing internal row address signals, a row address decoder unit responsive to the internal address signals and producing decode signals, a control signal buffer unit coupled between the first and second power voltage sources and supplied with an external control signal for producing a decode enable signal, and a word line driving unit responsive to the decode signals and selectively driving the word lines in the presence of the decode enable signal, wherein a monitoring unit is operative to monitor the power voltage level of one of the first and second power voltage sources and enables the control signal buffer unit to produce the decode enable signal when the power voltage level allows the internal address signals to become effective to the row address decoder unit so that any multiple selection of word lines never takes place.
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