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公开(公告)号：US20100207183A1
公开(公告)日：2010-08-19
申请号：US12510666
申请日：2009-07-28
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/1104 , H01L21/26586 , H01L27/11 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/66659
摘要： A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.
摘要翻译： 公开了一种控制晶体管的栅感应漏极漏电流的方法。 该方法包括在具有第一导电类型（P阱）的第一浓度的衬底的表面上形成电介质区域（516）。 在电介质区域上形成具有长度和宽度的栅极区域（500）。 在栅极区域的相对侧的衬底中形成具有第二导电类型（N +）的源极（512）和漏极（504）区域。 在源附近形成具有第一导电类型（P +）的第一杂质区（508）。 第一杂质区域具有大于第一浓度的第二浓度。
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公开(公告)号：US07384839B2
公开(公告)日：2008-06-10
申请号：US11239626
申请日：2005-09-29
IPC分类号： H01L21/8238
CPC分类号： H01L27/1104 , H01L21/26586 , H01L27/0207 , H01L27/11 , H01L29/1045 , H01L29/66659
摘要： A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.
摘要翻译： 公开了一种制造具有减少泄漏的SRAM单元的方法。 该方法包括在SRAM单元中制造不对称晶体管。 晶体管以不减小晶体管的漏极漏电流的方式是不对称的。 不对称传输晶体管的制造包括在具有第一导电类型的衬底的表面上形成电介质区域。 在电介质区域上形成具有长度和宽度的栅极区域。 具有第二导电类型的源极和漏极延伸区域形成在栅极区域的相对侧上的衬底中。 在源附近形成具有第一浓度和第一导电类型的第一杂质杂质区。 可以在漏极附近形成具有第二浓度和第一导电类型的第二袋杂质区域。 如果形成，则第二浓度小于第一浓度，减小了栅极引起的漏极漏电流。
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公开(公告)号：US20120261768A1
公开(公告)日：2012-10-18
申请号：US13478839
申请日：2012-05-23
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , H01L21/26586 , H01L27/11 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/66659
摘要： A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.
摘要翻译： 公开了一种控制晶体管的栅感应漏极漏电流的方法。 该方法包括在具有第一导电类型（P阱）的第一浓度的衬底的表面上形成电介质区域（516）。 在电介质区域上形成具有长度和宽度的栅极区域（500）。 在栅极区域的相对侧的衬底中形成具有第二导电类型（N +）的源极（512）和漏极（504）区域。 在源附近形成具有第一导电类型（P +）的第一杂质区（508）。 第一杂质区域具有大于第一浓度的第二浓度。
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公开(公告)号：US08216903B2
公开(公告)日：2012-07-10
申请号：US11238932
申请日：2005-09-29
IPC分类号： H01L21/336
CPC分类号： H01L27/1104 , H01L21/26586 , H01L27/11 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/66659
摘要： A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.
摘要翻译： 公开了一种控制晶体管的栅感应漏极漏电流的方法。 该方法包括在具有第一导电类型（P阱）的第一浓度的衬底的表面上形成电介质区域（516）。 在电介质区域上形成具有长度和宽度的栅极区域（500）。 在栅极区域的相对侧的衬底中形成具有第二导电类型（N +）的源极（512）和漏极（504）区域。 在源附近形成具有第一导电类型（P +）的第一杂质区（508）。 第一杂质区域具有大于第一浓度的第二浓度。
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公开(公告)号：US08211773B2
公开(公告)日：2012-07-03
申请号：US12510666
申请日：2009-07-28
IPC分类号： H01L21/336
CPC分类号： H01L27/1104 , H01L21/26586 , H01L27/11 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/66659
摘要： A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.
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公开(公告)号：US20080237745A1
公开(公告)日：2008-10-02
申请号：US12113770
申请日：2008-05-01
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , H01L21/26586 , H01L27/0207 , H01L27/11 , H01L29/1045 , H01L29/66659
摘要： A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.
摘要翻译： 公开了一种制造具有减少泄漏的SRAM单元的方法。 该方法包括在SRAM单元中制造不对称晶体管。 晶体管以不减小晶体管的漏极漏电流的方式是不对称的。 不对称传输晶体管的制造包括在具有第一导电类型的衬底的表面上形成电介质区域。 在电介质区域上形成具有长度和宽度的栅极区域。 具有第二导电类型的源极和漏极延伸区域形成在栅极区域的相对侧上的衬底中。 在源附近形成具有第一浓度和第一导电类型的第一杂质杂质区。 可以在漏极附近形成具有第二浓度和第一导电类型的第二袋杂质区域。 如果形成，则第二浓度小于第一浓度，减小了栅极引起的漏极漏电流。
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7.发明授权Method and system for contiguous proximity correction for semiconductor masks 有权用于半导体掩模的连续邻近校正的方法和系统公开(公告)号：US07341808B2
公开(公告)日：2008-03-11
申请号：US10895512
申请日：2004-07-20
CPC分类号： G03F1/36
摘要： According to one embodiment, a method for patterning a set of features for a semiconductor device includes providing a mask including a substrate and at least one pair of first and second main features disposed on a substrate. The method also includes positioning the mask over a layer of light-sensitive material, and exposing the mask to a light source. The mask also includes at least one sub-resolution feature connecting the first and second main features.
摘要翻译： 根据一个实施例，用于对半导体器件的一组特征进行构图的方法包括提供包括衬底的掩模和设置在衬底上的至少一对第一和第二主要特征。 该方法还包括将掩模定位在感光材料层上，并将掩模曝光到光源。 掩模还包括连接第一和第二主要特征的至少一个子分辨率特征。
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公开(公告)号：US07327591B2
公开(公告)日：2008-02-05
申请号：US10870355
申请日：2004-06-17
申请人： Kayvan Sadra , Theodore W. Houston
发明人： Kayvan Sadra , Theodore W. Houston
IPC分类号： G11C5/06
CPC分类号： H01L27/1104
摘要： A method of placing a cell in an array is disclosed. The method includes placing the cell a plurality of times (600, 602, 604) in a first array. The cell is also placed a plurality of times (606, 608, 610) in a second array. The second array is placed adjacent and offset from the first array by an offset distance (O2).
摘要翻译： 公开了将阵列放置在阵列中的方法。 该方法包括将单元多次（600,602,604）放置在第一阵列中。 单元还在第二阵列中放置多次（606,608,610）。 第二阵列被放置在与第一阵列相邻并偏移一个偏移距离（O 2 2 N）的位置。
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9.发明授权Application of post-pattern resist trim for reducing pocket-shadowing in SRAMs 有权用于减少SRAM中的口袋阴影的后图案抗蚀剂修整的应用公开(公告)号：US07132340B2
公开(公告)日：2006-11-07
申请号：US11018602
申请日：2004-12-21
申请人： Kayvan Sadra , Theodore W. Houston
发明人： Kayvan Sadra , Theodore W. Houston
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/31133 , H01L21/26586 , H01L29/66492 , H01L29/6659 , H01L29/7833
摘要： Methods (600, 700) are disclosed for minimizing the effect of pocket shadowing in the fabrication of an angled pocket implant (32) extending underlying a gate region (21) of a transistor (10), particularly in SRAM devices (400). The pocket shadowing is minimized by initially forming a relatively thick resist layer (810) overlying the semiconductor device (800), then the resist layer thickness (810y) is reduced (trimmed) to a reduced thickness (860y) by using a subsequent post-development dry or wet resist-reduction etch process (630, 730). The etch process (630, 730) also increases corner rounding (860r), thereby reducing pocket shadowing of the angled implant from nearby features or the resist (228, 328, 860). The pocket shadow reduction may be accomplished by first forming (610, 710) the relatively thick resist layer (810) overlying the semiconductor device (400, 800). The resist layer (860) is then wet and/or dry etched (630, 730) to trim the resist thickness (860y) and to round the corners (860r) of the resist (442, 860). In combination, these changes reduce shadowing of angled implants from nearby structures and resist edges. The method may further comprise a first implant (720) (e.g., an LDD implant) before the resist etch trim (730), and a second angled pocket implant (740) after the etch trim (730) to permit individually optimizing the resist thickness and CD for each implant. Thus, only one lithography step is required, while cross diffusion of the LDD implant is mitigated. Transistors (443 and 446, 448, or 830 and 840) formed in this manner may yield improved performance when incorporated into SRAM (400, 800) since the probability that such transistors will be more closely matched is increased.
摘要翻译： 公开了方法（600,700），用于最小化在制造在晶体管（10）的栅极区域（21）下方延伸的成角度的凹穴注入（32）的凹坑效应的影响，特别是在SRAM器件（400）中。 通过最初形成覆盖在半导体器件（800）上的相对较厚的抗蚀剂层（810），使光刻胶层的厚度（810μm）减小（修剪）至减小的厚度（860y） 显影后干或湿抗蚀剂还原蚀刻工艺（630,730）。 蚀刻工艺（630,730）还增加拐角圆角（860r），从而减少成角度的植入物从附近的特征或抗蚀剂（228,328,860）的阴影。 口袋阴影减少可以通过首先形成（610,710）覆盖半导体器件（400,800）的相对厚的抗蚀剂层（810）来实现。 然后将抗蚀剂层（860）湿法和/或干蚀刻（630,730）以修整抗蚀剂厚度（860y）并使抗蚀剂（442,860）的拐角（860r）圆弧。 结合起来，这些改变减少了来自附近结构和抵抗边缘的倾斜植入物的遮蔽。 该方法还可以包括在抗蚀剂蚀刻修整（730）之前的第一注入（720）（例如，LDD注入）和在蚀刻修整（730）之后的第二成角度的凹穴注入（740），以允许单独优化抗蚀剂厚度 和每个植入物的CD。 因此，仅需要一个光刻步骤，同时减轻LDD植入物的交叉扩散。 以这种方式形成的晶体管（443和446,448或830和840）可以在并入SRAM（400,800）时产生改进的性能，因为这种晶体管将更紧密匹配的概率增加。
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10.发明授权Body bias coordinator, method of coordinating a body bias and sub-circuit power supply employing the same 有权身体偏差协调器，协调身体偏压的方法和采用其的子电路电源公开(公告)号：US09124263B2
公开(公告)日：2015-09-01
申请号：US13116973
申请日：2011-05-26
IPC分类号： G05F1/10 , G05F3/02 , H03K19/00 , H03K17/687
CPC分类号： H03K19/0016 , H03K17/687 , H03K2217/0018 , H03K2217/0036
摘要： A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor.
摘要翻译： 身体偏置协调器被提供用于使用体区的晶体管。 在一个示例中，主体偏置协调器包括被配置为控制晶体管并使其可操作以在激活晶体管期间从源电压提供虚拟电源电压的控制单元。 身体偏置协调器还包括耦合到控制单元并被配置为在晶体管的激活期间将身体区域连接到虚拟电源电压的连接单元。 在替代实施例中，连接单元还被配置为在晶体管的非激活期间将身体区域连接到另一电压。
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