公开(公告)号：US20240338329A1

公开(公告)日：2024-10-10

申请号：US18747410

申请日：2024-06-18

Applicant: SiFive, Inc.

Inventor： Robert P. Adler ,  David Parry ,  Rick H. Y. Chen ,  Henry Cook

IPC: G06F13/16 ,  G06F12/0888

CPC classification number: G06F13/1668 ,  G06F12/0888 ,  G06F2212/603

Abstract: Disclosed are systems and methods that include accessing design parameters to configure an integrated circuit design. The integrated circuit design may include a transaction source or processing node to be included in an integrated circuit. The transaction source or processing node may be configured to transmit memory transactions to memory addresses. A compiler may compile the integrated circuit design with the transaction source or processing node to generate a design output. The design output may be configured to route memory transactions based on their targeting cacheable or non-cacheable memory addresses. The design output may be used to manufacture an integrated circuit.

公开(公告)号：US20240160449A1

公开(公告)日：2024-05-16

申请号：US18282728

申请日：2022-03-28

Applicant: SiFive, Inc.

Inventor： David Parry ,  Drew Barbier ,  Josh Smith ,  Alexandre Solomatnikov ,  Krste Asanovic

IPC: G06F9/32 ,  G06F9/30

CPC classification number: G06F9/327 ,  G06F9/30123

Abstract: Systems and methods are disclosed for a configurable interconnect address remapper with event detection. For example, an integrated circuit can include a processor core configured to execute instructions. The processor core includes region registers defined by a From Address range and a To Address, a register storing a number of regions defined in the integrated circuit, interrupt enable registers associated with each pair of region registers, and event flags associated with each pair of region registers; an interconnection system handling transactions from the processor core; an interconnect address remapper translating an address associated with a transaction using the one or more pair of region registers; and an interrupt controller receiving an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one raised event flags when at least one of the one or more pair of region registers matches the transaction address.