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1.发明申请Random Access Memory Featuring Reduced Leakage Current, and Method for Writing the Same 有权具有降低泄漏电流的随机存取存储器及其写入方法公开(公告)号：US20080212356A1
公开(公告)日：2008-09-04
申请号：US11661582
申请日：2005-08-18
IPC分类号： G11C17/00
CPC分类号： G11C17/12 , G11C2207/2227
摘要： The invention relates to a ROM memory cell comprising a first terminal connected to a word line, comprising a second terminal and comprising a third terminal, the second terminal being connected to a bit line and/or the third terminal being connected to a supply line for precharging the third terminal. The ROM memory cell according to the invention is distinguished by the fact that the same reference potential is in each case applied to the first terminal, the second terminal and/or the third terminal in a standby operating mode. The invention furthermore relates to a ROM memory component comprising such ROM memory cells, and to a method for reading from the ROM memory cell.
摘要翻译： 本发明涉及一种ROM存储单元，包括连接到字线的第一端子，包括第二端子并包括第三端子，第二端子连接到位线和/或第三端子连接到电源线 预充电第三个终端。 根据本发明的ROM存储器单元的特征在于，在待机操作模式中，相同的参考电位在每种情况下都应用于第一端子，第二端子和/或第三端子。 本发明还涉及一种包括这种ROM存储器单元的ROM存储器组件，以及一种用于从ROM存储单元读取的方法。
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2.发明授权ROM memory component featuring reduced leakage current, and method for writing the same 有权具有减少漏电流的ROM存储器组件及其写入方法公开(公告)号：US07633787B2
公开(公告)日：2009-12-15
申请号：US11661582
申请日：2005-08-18
IPC分类号： G11C17/00
CPC分类号： G11C17/12 , G11C2207/2227
摘要： The invention relates to a ROM memory cell comprising a first terminal connected to a word line, comprising a second terminal and comprising a third terminal, the second terminal being connected to a bit line and/or the third terminal being connected to a supply line for precharging the third terminal. The ROM memory cell according to the invention is distinguished by the fact that the same reference potential is in each case applied to the first terminal, the second terminal and/or the third terminal in a standby operating mode. The invention furthermore relates to a ROM memory component comprising such ROM memory cells, and to a method for reading from the ROM memory cell.
摘要翻译： 本发明涉及一种ROM存储单元，包括连接到字线的第一端子，包括第二端子并包括第三端子，第二端子连接到位线和/或第三端子连接到电源线 预充电第三个终端。 根据本发明的ROM存储器单元的特征在于，在待机操作模式中，相同的参考电位在每种情况下都应用于第一端子，第二端子和/或第三端子。 本发明还涉及一种包括这种ROM存储器单元的ROM存储器组件，以及一种用于从ROM存储单元读取的方法。
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3.发明申请Read-out circuit for or in a Rom memory; Rom memory and method for reading the Rom memory 有权ROM存储器中的读取电路; Rom内存和读取Rom内存的方法公开(公告)号：US20080031054A1
公开(公告)日：2008-02-07
申请号：US11803852
申请日：2007-05-16
IPC分类号： G11C7/10
摘要： A read-out circuit for or in a ROM memory, comprises an input, a comparator circuit, a threshold setting, and a control signal generator for driving the threshold setting generator. A read signal can be coupled into the input. The read signal, depending on the information contained in the read signal, comprises a high signal level relative to a reference potential or a low signal level relative to a reference potential. The comparator circuit compares the read signal with a settable threshold, the threshold setting circuit is designed for setting the threshold of the comparator circuit relative to the high and low signal levels, and the control signal generator generates a control signal similar to the read signal.
摘要翻译： 用于或在ROM存储器中的读出电路包括用于驱动阈值设置发生器的输入，比较器电路，阈值设置和控制信号发生器。 读信号可以耦合到输入端。 取决于读取信号中包含的信息的读取信号包括相对于参考电位的高信号电平或相对于参考电位的低信号电平。 比较器电路将读取信号与可设置的阈值进行比较，阈值设置电路被设计用于相对于高和低信号电平设置比较器电路的阈值，并且控制信号发生器产生类似于读取信号的控制信号。
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4.发明授权Read-out circuit for or in a ROM memory; ROM memory and method for reading the ROM memory 有权ROM存储器中或其中的读出电路; ROM存储器和用于读取ROM存储器的方法公开(公告)号：US07738305B2
公开(公告)日：2010-06-15
申请号：US11803852
申请日：2007-05-16
IPC分类号： G11C7/02
摘要： A read-out circuit for or in a ROM memory, comprises an input, a comparator circuit, a threshold setting, and a control signal generator for driving the threshold setting generator. A read signal can be coupled into the input. The read signal, depending on the information contained in the read signal, comprises a high signal level relative to a reference potential or a low signal level relative to a reference potential. The comparator circuit compares the read signal with a settable threshold, the threshold setting circuit is designed for setting the threshold of the comparator circuit relative to the high and low signal levels, and the control signal generator generates a control signal similar to the read signal.
摘要翻译： 用于或在ROM存储器中的读出电路包括用于驱动阈值设置发生器的输入，比较器电路，阈值设置和控制信号发生器。 读信号可以耦合到输入端。 取决于读取信号中包含的信息的读取信号包括相对于参考电位的高信号电平或相对于参考电位的低信号电平。 比较器电路将读取信号与可设置的阈值进行比较，阈值设置电路被设计用于相对于高和低信号电平设置比较器电路的阈值，并且控制信号发生器产生类似于读取信号的控制信号。
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公开(公告)号：US07366002B2
公开(公告)日：2008-04-29
申请号：US11267491
申请日：2005-11-04
IPC分类号： G11C17/00
CPC分类号： G11C7/1048 , G11C7/08 , G11C7/12 , G11C16/28 , G11C17/12 , G11C2207/005
摘要： It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigned to one of the bitlines connected to the column multiplexer, in dependence on whether or not the assignment of a first state and of a second state of memory cells, connected to the bitline, to a binary value “0” and to a binary value “1” is inverted for the respective bitline. The connection points are connected to a common nodal point via switching means. The switching means are activated through control signals of the column multiplexer. Selection signals for activating inverter means, in order to effect a selective inversion of values read out from the memory cells, are generated in dependence on the signal level at the common nodal point. A precharging of the common nodal point is preferably effected between to read-out operations in each case, for which purpose precharging switching means are provided.
摘要翻译： 提出将位线反转编码数据一体地存储在存储装置的列多路复用器的结构中。 为此，在连接点上有选择地提供与预定义电位的连接，连接点根据是否分配第一状态和第二状态的存储器分别分配给连接到列多路复用器的位线之一 连接到位线的单元对于二进制值“0”和二进制值“1”反转。 连接点通过开关装置连接到公共节点。 切换装置通过列多路复用器的控制信号被激活。 根据公共节点处的信号电平，产生用于激活反相器装置的选择信号，以便实现从存储器单元读出的值的选择性反转。 优选地，在每种情况下对读出操作之间进行公共节点的预充电，为此，提供预充电开关装置。
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公开(公告)号：US20060133128A1
公开(公告)日：2006-06-22
申请号：US11267491
申请日：2005-11-04
CPC分类号： G11C7/1048 , G11C7/08 , G11C7/12 , G11C16/28 , G11C17/12 , G11C2207/005
摘要： It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigned to one of the bitlines connected to the column multiplexer, in dependence on whether or not the assignment of a first state and of a second state of memory cells, connected to the bitline, to a binary value “0” and to a binary value “1” is inverted for the respective bitline. The connection points are connected to a common nodal point via switching means. The switching means are activated through control signals of the column multiplexer. Selection signals for activating inverter means, in order to effect a selective inversion of values read out from the memory cells, are generated in dependence on the signal level at the common nodal point. A precharging of the common nodal point is preferably effected between to read-out operations in each case, for which purpose precharging switching means are provided.
摘要翻译： 提出将位线反转编码数据一体地存储在存储装置的列多路复用器的结构中。 为此，在连接点上有选择地提供与预定义电位的连接，连接点根据是否分配第一状态和第二状态存储器分别分配给连接到列多路复用器的位线之一 连接到位线的单元对于二进制值“0”和二进制值“1”反转。 连接点通过开关装置连接到公共节点。 切换装置通过列多路复用器的控制信号被激活。 根据公共节点处的信号电平，产生用于激活反相器装置的选择信号，以便实现从存储器单元读出的值的选择性反转。 优选地，在每种情况下对读出操作之间进行公共节点的预充电，为此，提供预充电开关装置。
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公开(公告)号：US07403432B2
公开(公告)日：2008-07-22
申请号：US11358374
申请日：2006-02-21
IPC分类号： G11C7/10
摘要： A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells. The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells. The read-out circuit has a volatile signal memory, the inputs of which are connected to the read outputs of the memory cells.
摘要翻译： 公开了一种读出电路，其中电路从包括两个非易失性存储器单元的存储器单元中读出信息。 单元具有不同的编程状态，并且存储器单元的存储器信息由两个存储器单元的编程状态给出。 读出电路具有易失性信号存储器，其输入连接到存储器单元的读取输出。
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公开(公告)号：US20060203585A1
公开(公告)日：2006-09-14
申请号：US11358374
申请日：2006-02-21
IPC分类号： G11C7/00
摘要： A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells (F2, F3). The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells (F2, F3). The read-out circuit has a volatile signal memory (INV4, INV5), the inputs of which are connected to the read outputs of the memory cells (F2, F3).
摘要翻译： 公开了一种读出电路，其中电路从包括两个非易失性存储单元（F 2，F 3）的存储单元中读出信息。 单元具有不同的编程状态，存储单元的存储器信息由两个存储单元（F 2，F 3）的编程状态给出。 读出电路具有易失性信号存储器（INV 4，INV 5），其输入端连接到存储单元（F 2，F 3）的读出端。
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公开(公告)号：US07099218B2
公开(公告)日：2006-08-29
申请号：US10429149
申请日：2003-05-02
CPC分类号： G11C11/419 , G11C7/062 , G11C2207/063
摘要： A differential current evaluation circuit has a differential amplifier and a circuit for setting an input resistance of the current evaluation circuit. The circuit is connected to the outputs and the inputs of the differential amplifier and to signal lines. A sense amplifier circuit has a circuit section, in which a signal is available at an output in a temporally continuous manner even if, after the deactivation of the circuit connected upstream, a signal, in particular a signal supplied by the current evaluation circuit, is no longer present at its input. The differential current evaluation circuit and the sense amplifier circuit are disposed in a circuit configuration for reading out and evaluating a memory state of a semiconductor memory cell. The current evaluation circuit can be activated by a circuit section for automatic deactivation before a read operation and be automatically deactivated directly after the read operation has ended.
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公开(公告)号：US07403442B2
公开(公告)日：2008-07-22
申请号：US11331408
申请日：2006-01-12
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C8/08
摘要： The invention relates to a driver circuit for driving a word line of a memory. The driver circuit comprises a driver unit for deactivating the word line after an access to a memory cell, a discharging means for discharging the word line, and a signal generator that generates two control signals. A first signal triggers the driver unit to deactivate the word line and triggers the discharging means to discharge the word line. A second signal triggers the discharging mean to stop discharging the word line.
摘要翻译： 本发明涉及用于驱动存储器的字线的驱动电路。 驱动器电路包括用于在访问存储单元之后去激活字线的驱动器单元，用于放电字线的放电装置和产生两个控制信号的信号发生器。 第一信号触发驱动器单元去激活字线并触发放电装置放电字线。 第二个信号触发放电平均以停止字线的放电。
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