公开(公告)号：US20220336408A1

公开(公告)日：2022-10-20

申请号：US17640937

申请日：2020-09-03

Applicant: Siemens Aktiengesellschaft

Inventor： Nora Jeske ,  Bernd Müller ,  Christian Nachtigall-Schellenberg ,  Jörg Strogies ,  Klaus Wilke

IPC: H01L23/00 ,  H01L21/56

Abstract: Various embodiments of the teachings herein include a semifinished product for use in the populating of a power electronics component by a connecting method. The product includes an electrically insulating prepreg frame electrically insulated. The prepreg frame is configured for surrounding an applied connecting material at a metallized installation site during the population. A material of the prepreg frame enables simultaneous processability of electrical connection and electrical insulation by compression of the insulation material in the form of the semifinished product since the processing parameters of the electrical connecting material and the semifinished product are compatible.

公开(公告)号：US20220285311A1

公开(公告)日：2022-09-08

申请号：US17630030

申请日：2020-06-15

Applicant: Siemens Aktiengesellschaft

Inventor： Matthias Heimann ,  Bernd Müller ,  Christian Nachtigall-Schellenberg ,  Jörg Strogies ,  Klaus Wilke

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683

Abstract: Various embodiments include a method for installing an electronic assembly having a die and a substrate with a reference plane. The method may include: providing a product carrier having recesses with varying dimensions different from one another; and arranging planar molded parts, joining materials, and the die on the product carrier. The die is in electrical contact with at least one planar molded part and at least one joining material. The method further includes forming functional elements from the planar molded parts and/or the die and the joining materials, the functional elements supporting the substrate and electrically contacting the reference plane.

公开(公告)号：US20230215838A1

公开(公告)日：2023-07-06

申请号：US17928318

申请日：2021-05-19

Applicant: Siemens Aktiengesellschaft

Inventor： Bernd Müller ,  Christian Nachtigall-Schellenberg ,  Jörg Strogies ,  Klaus Wilke

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/92 ,  H01L24/33 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L21/563 ,  H01L23/3185 ,  H01L2224/33183 ,  H01L2224/3303 ,  H01L2224/29191 ,  H01L2924/0715 ,  H01L2224/29291 ,  H01L2224/29387 ,  H01L2224/29388 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/9211 ,  H01L2224/81201 ,  H01L2224/83201 ,  H01L2224/8184 ,  H01L2224/83102 ,  H01L23/585

Abstract: Various embodiments of the teachings herein include a method for joining and insulating a power electronic semiconductor component with contact surfaces to a substrate. In some embodiments, the method includes: preparing the substrate with a metallization defining an installation slot having joining material, wherein the substrate comprises an organic or a ceramic wiring support; arranging an electrically insulating film and the semiconductor component on the substrate, such that the contact surfaces of the semiconductor component facing the substrate are omitted from the film and regions of the semiconductor component exposed by the contact surfaces are insulated at least in part by the film from the substrate and from the contact surfaces; and joining the semiconductor component to the substrate and electrically insulating the semiconductor component at least in part by the film in one step.