公开(公告)号：US08836033B1

公开(公告)日：2014-09-16

申请号：US13357796

申请日：2012-01-25

申请人： Silai Krishnaswamy ,  Joseph Payne ,  Jeffrey Hartman

发明人： Silai Krishnaswamy ,  Joseph Payne ,  Jeffrey Hartman

IPC分类号： G02B5/30

CPC分类号： B82Y30/00 ,  B82Y40/00

摘要： Embodiments of a method and apparatus for removing metallic nanotubes without transferring CNTs from one substrate to another substrate provide two methods of transferring a thin layer of crystalline ST-cut quartz wafer to the surface of a carrier silicon wafer for subsequent CNT growth, without resorting to CNT transfer. In other words, embodiments of a method and apparatus allow CNTs to be grown on the same substrate that metallic nanotube removal is performed, therefore eliminating the costly and messy step of transferring CNTs from one substrate to another. This is achieved through a residual thin layer of crystalline ST-cut quartz layer on a silicon wafer. The ST-cut quartz wafer promotes aligned growth of CNTs, while the underlying silicon wafer allows backgate burnout.

摘要翻译： 用于去除金属纳米管而不将CNT从一个衬底转移到另一个衬底的方法和设备的实施例提供了将晶体ST切割石英晶片的薄层转移到载体硅晶片的表面以用于随后的CNT生长的两种方法，而不诉诸于 CNT转移。 换句话说，方法和装置的实施例允许CNT在相同的衬底上生长金属纳米管去除，因此消除了将碳纳米管从一个衬底转移到另一个衬底的昂贵和混乱的步骤。 这通过在硅晶片上的晶体ST切割石英层的残留薄层来实现。 ST切割的石英晶片促进CNT的对准生长，而下面的硅晶片允许背栅板烧尽。

公开(公告)号：US20060286767A1

公开(公告)日：2006-12-21

申请号：US11154641

申请日：2005-06-17

申请人： Rowland Clarke ,  Erica Elvey ,  Silai Krishnaswamy ,  Jeffrey Hartman

发明人： Rowland Clarke ,  Erica Elvey ,  Silai Krishnaswamy ,  Jeffrey Hartman

IPC分类号： H01L21/30

CPC分类号： H01L21/76256 ,  H01L21/3065 ,  Y10S438/977

摘要： First and second semiconductor wafers are bonded together, with at least one of the wafers having a first layer of silicon, an intermediate oxide layer and a second layer of silicon. The first silicon layer is initially mechanically reduced by around 80% to 90% of its thickness. The remaining silicon layer is further reduced by a plasma etch which may leave an uneven thickness. With appropriate masking the uneven thickness is made even by a second plasma etch. Remaining silicon is removed by a dry etch with XeF2 or BrF3 to expose the intermediate oxide layer. Prior to bonding the semiconductor wafers may be provided with various semiconductor devices to which electrical connections are made through conducting vias formed through the exposed intermediate oxide layer.

摘要翻译： 第一和第二半导体晶片被结合在一起，其中至少一个晶片具有第一层硅，中间氧化物层和第二硅层。 第一硅层最初机械地还原其厚度的大约80％至90％。 剩余的硅层通过等离子体蚀刻进一步减小，其可能留下不均匀的厚度。 通过适当的掩蔽，即使通过第二等离子体蚀刻也可以形成不均匀的厚度。 通过用XeF 2或BrF 3 3的干蚀刻除去剩余的硅，以暴露中间氧化物层。 在接合之前，半导体晶片可以设置有各种半导体器件，通过通过暴露的中间氧化物层形成的通孔来形成电连接。

公开(公告)号：US20060186761A1

公开(公告)日：2006-08-24

申请号：US10996604

申请日：2004-11-26

申请人： Susan Trolier-McKinstry ,  Eunki Hong ,  Carl Freidhoff ,  Silai Krishnaswamy

发明人： Susan Trolier-McKinstry ,  Eunki Hong ,  Carl Freidhoff ,  Silai Krishnaswamy

IPC分类号： H01L41/18

CPC分类号： H01L41/0973 ,  F04B43/046 ,  H01L41/047 ,  H01L41/1876 ,  H01L41/257 ,  H01L41/317

摘要： The disclosed invention relates to achieving micromachined piezoelectrically-actuated diaphragms. The piezoelectric diaphragm includes a central, inactive electrode free region and an annular shaped interdigitated electrode adjacent to the outer periphery of the central region. The diaphragm also may have an inactive annular, electrode free region and an active central, interdigitated electrode region. The diaphragms may be used in, such as, miniature pumps. The pumps may include a plurality of chambers to generate peristaltic pumping of fluids.

摘要翻译： 所公开的发明涉及实现微加工的压电致动隔膜。 压电振膜包括中心的非活性电极自由区和与中心区的外周相邻的环形交错电极。 隔膜还可以具有无活性环形，无电极区域和活性中心交叉电极区域。 隔膜可用于例如微型泵中。 泵可以包括多个腔室以产生流体的蠕动泵送。