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    Charge pump calibration for dual-path phase-locked loop
    1.
    发明授权
    Charge pump calibration for dual-path phase-locked loop 有权
    双路锁相环的电荷泵校准

    公开(公告)号：US09225345B2

    公开(公告)日：2015-12-29

    申请号：US14371973

    申请日：2014-01-30

    Applicant: SILICON IMAGE, INC.

    Inventor： Baoli Tong ,  Fei Song ,  Xiaozhi Lin ,  Xiaofeng Wang

    IPC: H03L7/06 ,  H03L7/089 ,  H03L7/099

    CPC classification number: H03L7/0898 ,  H03L7/0893 ,  H03L7/0992 ,  H03L7/0994

    Abstract: Embodiments of the invention are generally directed to charge pump calibration for a dual-path phase-locked loop circuit. An embodiment of an apparatus includes a phase frequency detector; an integral path including a first charge pump; a proportional path including a second charge pump; and a calibration mechanism for the first charge pump and the second charge pump, the calibration mechanism including a phase detector to detect whether a reference clock signal or a feedback clock signal is leading or lagging in phase and to generate a signal indicating which clock signal is leading or lagging, a first memory element and a second memory element to store the signal from the phase detector, a first control logic to adjust current for the first charge pump based on the value stored in the first memory element, and a second control logic to adjust current for the second charge pump based on the value stored in the second memory element.

    Abstract translation: 本发明的实施例一般涉及用于双路锁相环电路的电荷泵校准。 装置的实施例包括相位频率检测器; 包括第一电荷泵的整体路径; 包括第二电荷泵的比例路径; 以及用于所述第一电荷泵和所述第二电荷泵的校准机构，所述校准机构包括相位检测器，用于检测参考时钟信号或反馈时钟信号是否在同相中前进或滞后，并产生指示哪个时钟信号为 第一存储器元件和第二存储器元件，用于存储来自相位检测器的信号;第一控制逻辑，用于基于存储在第一存储器元件中的值来调整第一电荷泵的电流;以及第二控制逻辑 基于存储在第二存储元件中的值来调整第二电荷泵的电流。

    Charge Pump Calibration for Dual-Path Phase-Locked Loop
    4.
    发明申请
    Charge Pump Calibration for Dual-Path Phase-Locked Loop 有权
    双路锁相环电荷泵校准

    公开(公告)号：US20150214966A1

    公开(公告)日：2015-07-30

    申请号：US14371973

    申请日：2014-01-30

    Applicant: SILICON IMAGE, INC.

    Inventor： Baoli Tong ,  Fei Song ,  Xiaozhi Lin ,  Xiaofeng Wang

    IPC: H03L7/089 ,  H03L7/099

    CPC classification number: H03L7/0898 ,  H03L7/0893 ,  H03L7/0992 ,  H03L7/0994

    Abstract: Embodiments of the invention are generally directed to charge pump calibration for a dual-path phase-locked loop circuit. An embodiment of an apparatus includes a phase frequency detector; an integral path including a first charge pump; a proportional path including a second charge pump; and a calibration mechanism for the first charge pump and the second charge pump, the calibration mechanism including a phase detector to detect whether a reference clock signal or a feedback clock signal is leading or lagging in phase and to generate a signal indicating which clock signal is leading or lagging, a first memory element and a second memory element to store the signal from the phase detector, a first control logic to adjust current for the first charge pump based on the value stored in the first memory element, and a second control logic to adjust current for the second charge pump based on the value stored in the second memory element.

    Abstract translation: 本发明的实施例一般涉及用于双路锁相环电路的电荷泵校准。 装置的实施例包括相位频率检测器; 包括第一电荷泵的整体路径; 包括第二电荷泵的比例路径; 以及用于所述第一电荷泵和所述第二电荷泵的校准机构，所述校准机构包括相位检测器，用于检测参考时钟信号或反馈时钟信号是否在同相中前进或滞后，并产生指示哪个时钟信号为 第一存储器元件和第二存储器元件，用于存储来自相位检测器的信号;第一控制逻辑，用于基于存储在第一存储器元件中的值来调整第一电荷泵的电流;以及第二控制逻辑 基于存储在第二存储元件中的值来调整第二电荷泵的电流。

    COMPENSATION SCHEME FOR MHL COMMON MODE CLOCK SWING
    6.
    发明申请
    COMPENSATION SCHEME FOR MHL COMMON MODE CLOCK SWING 有权
    MHL共通模式时钟振荡补偿方案

    公开(公告)号：US20150288397A1

    公开(公告)日：2015-10-08

    申请号：US14118832

    申请日：2012-12-28

    Applicant: Silicon Image, Inc.

    Inventor： Xiaozhi Lin ,  Fei Song ,  Gyudong Kim ,  Chwei-po Chew ,  Min-Kyu Kim

    IPC: H04B1/12 ,  H04L27/26

    CPC classification number: H04B1/123 ,  H03F3/45475 ,  H03F3/45717 ,  H03F2203/45418 ,  H04L27/2691

    Abstract: Embodiments of the invention are generally directed to compensation for common mode signal swing. An embodiment of an apparatus includes a connector for the transfer of the data, the connector including connections for a first set of one or more conductors; a receiver for the reception of data via the connector, the received data including a first signal and a second signal transmitted via the set of one or more conductors, the second signal being a common mode signal modulating the first signal, the receiver including an amplifier to amplify the received data with a positive gain; and a common mode compensation circuit to compensate for a voltage swing of the common mode signal in the amplified received data. The common mode compensation circuit is to sense the common mode signal, amplify the sensed common mode signal with a negative gain, and feed back the amplified common mode to output nodes of the receiver.

    Abstract translation: 本发明的实施例通常涉及对共模信号摆幅的补偿。 装置的实施例包括用于传送数据的连接器，连接器包括用于第一组一个或多个导体的连接; 用于经由连接器接收数据的接收器，所接收的数据包括通过一组或多个导体发送的第一信号和第二信号，第二信号是调制第一信号的共模信号，接收器包括放大器 以正增益放大接收到的数据; 以及用于补偿放大的接收数据中的共模信号的电压摆幅的共模补偿电路。 共模补偿电路用于检测共模信号，以负增益放大感测的共模信号，并将放大的共模反馈到接收器的输出节点。

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