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公开(公告)号：US10764995B2
公开(公告)日：2020-09-01
申请号：US15867924
申请日：2018-01-11
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Jin-Wei You , Chun-Lung Chen
Abstract: A method for fabricating a substrate structure is provided, which includes the steps of: disposing at least a strengthening member on a carrier; sequentially forming a first circuit layer and a dielectric layer on the carrier, wherein the strengthening member is embedded in the dielectric layer; forming a second circuit layer on the dielectric layer; removing the carrier; and forming an insulating layer on the first circuit layer and the second circuit layer. The strengthening member facilitates to reduce thermal warping of the substrate structure.
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公开(公告)号：US20180139840A1
公开(公告)日：2018-05-17
申请号：US15867924
申请日：2018-01-11
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Jin-Wei You , Chun-Lung Chen
CPC classification number: H05K1/0271 , H05K3/007 , H05K3/184 , H05K3/4682 , H05K2201/0187 , H05K2201/096 , H05K2203/0709
Abstract: A method for fabricating a substrate structure is provided, which includes the steps of: disposing at least a strengthening member on a carrier; sequentially forming a first circuit layer and a dielectric layer on the carrier, wherein the strengthening member is embedded in the dielectric layer; forming a second circuit layer on the dielectric layer; removing the carrier; and forming an insulating layer on the first circuit layer and the second circuit layer. The strengthening member facilitates to reduce thermal warping of the substrate structure.
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Patent Agency Ranking
公开(公告)号：US09907161B2
公开(公告)日：2018-02-27
申请号：US14833101
申请日：2015-08-23
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Jin-Wei You , Chun-Lung Chen
CPC classification number: H05K1/0271 , H05K3/007 , H05K3/184 , H05K3/4682 , H05K2201/0187 , H05K2201/096 , H05K2203/0709
Abstract: A method for fabricating a substrate structure is provided, which includes the steps of: disposing at least a strengthening member on a carrier; sequentially forming a first circuit layer and a dielectric layer on the carrier, wherein the strengthening member is embedded in the dielectric layer; forming a second circuit layer on the dielectric layer; removing the carrier; and forming an insulating layer on the first circuit layer and the second circuit layer. The strengthening member facilitates to reduce thermal warping of the substrate structure.
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公开(公告)号：US09666548B2
公开(公告)日：2017-05-30
申请号：US14683716
申请日：2015-04-10
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chih-Sheng Lin , Chun-Lung Chen , Hsin-Hung Lee
CPC classification number: H01L24/11 , C23C14/34 , C25D5/02 , C25D7/12 , H01L24/06 , H01L24/14 , H01L2224/03001 , H01L2224/0401 , H01L2224/11001 , H01L2924/01029 , H05K1/111 , H05K3/4007 , H05K2201/0338 , H05K2201/0367 , Y10T29/49124
Abstract: A connection structure for a substrate is provided. The substrate has a plurality of connection pads and an insulation protection layer with the connection pads being exposed therefrom. The connection structure includes a metallic layer formed on an exposed surface of each of the connection pads and extending to the insulation protection layer, and a plurality of conductive bumps disposed on the metallic layer and spaced apart from one another at a distance less than or equal to 80 μm, each of conductive bumps having a width less than a width of each of the connection pads. Since the metallic layer covers the exposed surfaces of the connection pads completely, a colloid material will not flow to a surface of the connection pads during a subsequent underfilling process of a flip-chip process. Therefore, the colloid material will not be peeled off from the connection pads.
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公开(公告)号：US20150214169A1
公开(公告)日：2015-07-30
申请号：US14683716
申请日：2015-04-10
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chih-Sheng Lin , Chun-Lung Chen , Hsin-Hung Lee
CPC classification number: H01L24/11 , C23C14/34 , C25D5/02 , C25D7/12 , H01L24/06 , H01L24/14 , H01L2224/03001 , H01L2224/0401 , H01L2224/11001 , H01L2924/01029 , H05K1/111 , H05K3/4007 , H05K2201/0338 , H05K2201/0367 , Y10T29/49124
Abstract: A connection structure for a substrate is provided. The substrate has a plurality of connection pads and an insulation protection layer with the connection pads being exposed therefrom. The connection structure includes a metallic layer formed on an exposed surface of each of the connection pads and extending to the insulation protection layer, and a plurality of conductive bumps disposed on the metallic layer and spaced apart from one another at a distance less than or equal to 80 μm, each of conductive bumps having a width less than a width of each of the connection pads. Since the metallic layer covers the exposed surfaces of the connection pads completely, a colloid material will not flow to a surface of the connection pads during a subsequent underfilling process of a flip-chip process. Therefore, the colloid material will not be peeled off from the connection pads.
Abstract translation: 提供了一种用于基板的连接结构。 衬底具有多个连接焊盘和绝缘保护层，其中连接焊盘从其暴露。 连接结构包括形成在每个连接焊盘的暴露表面上并延伸到绝缘保护层的金属层，以及设置在金属层上并以小于或等于的距离彼此间隔开的多个导电凸块 每个导电凸块的宽度小于每个连接焊盘的宽度。 由于金属层完全覆盖连接焊盘的暴露表面，所以在随后的倒装芯片工艺的底部填充过程中，胶体材料将不会流到连接焊盘的表面。 因此，胶体材料不会从连接垫剥离。
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6.发明申请CONNECTION STRUCTURE FOR A SUBSTRATE AND A METHOD OF FABRICATING THE CONNECTION STRUCTURE 审中-公开一种基板的连接结构和一种制作连接结构的方法公开(公告)号：US20140131072A1
公开(公告)日：2014-05-15
申请号：US13729710
申请日：2012-12-28
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Chih-Sheng Lin , Chun-Lung Chen , Hsin-Hung Lee
CPC classification number: H01L24/11 , C23C14/34 , C25D5/02 , C25D7/12 , H01L24/06 , H01L24/14 , H01L2224/03001 , H01L2224/0401 , H01L2224/11001 , H01L2924/01029 , H05K1/111 , H05K3/4007 , H05K2201/0338 , H05K2201/0367 , Y10T29/49124
Abstract: A connection structure for a substrate is provided. The substrate has a plurality of connection pads and an insulation protection layer with the connection pads being exposed therefrom. The connection structure includes a metallic layer formed on an exposed surface of each of the connection pads and extending to the insulation protection layer, and a plurality of conductive bumps disposed on the metallic layer and spaced apart from one another at a distance less than or equal to 80 μm, each of conductive bumps having a width less than a width of each of the connection pads. Since the metallic layer covers the exposed surfaces of the connection pads completely, a colloid material will not flow to a surface of the connection pads during a subsequent underfilling process of a flip-chip process. Therefore, the colloid material will not be peeled off from the connection pads.
Abstract translation: 提供了一种用于基板的连接结构。 衬底具有多个连接焊盘和绝缘保护层，其中连接焊盘从其暴露。 连接结构包括形成在每个连接焊盘的暴露表面上并延伸到绝缘保护层的金属层，以及设置在金属层上并以小于或等于的距离彼此间隔开的多个导电凸块 每个导电凸块的宽度小于每个连接焊盘的宽度。 由于金属层完全覆盖连接焊盘的暴露表面，所以在随后的倒装芯片工艺的底部填充过程中，胶体材料将不会流到连接焊盘的表面。 因此，胶体材料不会从连接垫剥离。
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公开(公告)号：US20160128184A1
公开(公告)日：2016-05-05
申请号：US14833101
申请日：2015-08-23
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Jin-Wei You , Chun-Lung Chen
CPC classification number: H05K1/0271 , H05K3/007 , H05K3/184 , H05K3/4682 , H05K2201/0187 , H05K2201/096 , H05K2203/0709
Abstract: A method for fabricating a substrate structure is provided, which includes the steps of: disposing at least a strengthening member on a carrier; sequentially forming a first circuit layer and a dielectric layer on the carrier, wherein the strengthening member is embedded in the dielectric layer; forming a second circuit layer on the dielectric layer; removing the carrier; and forming an insulating layer on the first circuit layer and the second circuit layer. The strengthening member facilitates to reduce thermal warping of the substrate structure.
Abstract translation: 提供了一种用于制造衬底结构的方法，其包括以下步骤：在载体上设置至少一个加强构件; 在所述载体上依次形成第一电路层和电介质层，其中所述强化构件嵌入在所述电介质层中; 在所述电介质层上形成第二电路层; 移除载体; 以及在所述第一电路层和所述第二电路层上形成绝缘层。 加强构件有助于减少基底结构的热翘曲。
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