公开(公告)号：US20150028913A1

公开(公告)日：2015-01-29

申请号：US14074187

申请日：2013-11-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kuang-Ching Fan ,  Hsin-Hung Lee

IPC: G01R31/26

CPC classification number: G01R31/2853 ,  G01R31/2865

Abstract: The present invention proposes a testing method for testing a semiconductor element, including: providing a semiconductor element having a first surface on which a first testing area is formed and a second surface on which a second testing surface is formed; placing the semiconductor element on a plane surface, allowing any one of the first surface and the second surface to be in no parallel to the plane surface; and electrically connecting a testing apparatus to the first testing area and the second testing area of the semiconductor element. The semiconductor element is placed in a non-horizontal manner on the testing apparatus, which makes contact with the two opposing surfaces of the semiconductor element in a horizontal way without directly exerting a downward force against the surface of the semiconductor element, thereby preventing the semiconductor element from damages.

Abstract translation: 本发明提出一种半导体元件的测试方法，包括：提供具有形成有第一测试区域的第一表面的半导体元件和形成有第二测试表面的第二表面; 将所述半导体元件放置在平面上，使得所述第一表面和所述第二表面中的任何一个不平行于所述平面; 并将测试装置电连接到半导体元件的第一测试区域和第二测试区域。 半导体元件以非水平的方式放置在测试装置上，其以水平方式与半导体元件的两个相对的表面接触而不会直接向半导体元件的表面施加向下的力，从而防止半导体元件 元素不受损害。

公开(公告)号：US09666548B2

公开(公告)日：2017-05-30

申请号：US14683716

申请日：2015-04-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Sheng Lin ,  Chun-Lung Chen ,  Hsin-Hung Lee

IPC: C25D5/02 ,  H01L23/00 ,  H05K1/11 ,  H05K3/40 ,  C23C14/34 ,  C25D7/12

CPC classification number: H01L24/11 ,  C23C14/34 ,  C25D5/02 ,  C25D7/12 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/03001 ,  H01L2224/0401 ,  H01L2224/11001 ,  H01L2924/01029 ,  H05K1/111 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0367 ,  Y10T29/49124

Abstract: A connection structure for a substrate is provided. The substrate has a plurality of connection pads and an insulation protection layer with the connection pads being exposed therefrom. The connection structure includes a metallic layer formed on an exposed surface of each of the connection pads and extending to the insulation protection layer, and a plurality of conductive bumps disposed on the metallic layer and spaced apart from one another at a distance less than or equal to 80 μm, each of conductive bumps having a width less than a width of each of the connection pads. Since the metallic layer covers the exposed surfaces of the connection pads completely, a colloid material will not flow to a surface of the connection pads during a subsequent underfilling process of a flip-chip process. Therefore, the colloid material will not be peeled off from the connection pads.

公开(公告)号：US20160181126A1

公开(公告)日：2016-06-23

申请号：US15054845

申请日：2016-02-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tai-Tsung Hsu ,  Cheng-Yu Chiang ,  Miao-Wen Chen ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L21/56 ,  H01L21/428 ,  H01L23/58 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L21/56 ,  H01L21/428 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/552 ,  H01L23/585 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/1815

Abstract: A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided.

Abstract translation: 提供一种多芯片封装结构，包括具有接地结构的基板; 两个半导体元件设置在基板上并与其电连接; 形成在所述基板上并封装半导体元件的密封剂，其中所述密封剂具有形成在所述半导体元件之间的多个圆形孔; 以及形成在每个圆孔中的电磁屏蔽结构，并连接到接地结构以实现电磁屏蔽效果。 还提供了一种用于形成多芯片封装的方法。

公开(公告)号：US20150214169A1

公开(公告)日：2015-07-30

申请号：US14683716

申请日：2015-04-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Sheng Lin ,  Chun-Lung Chen ,  Hsin-Hung Lee

IPC: H01L23/00 ,  C25D7/12 ,  C23C14/34 ,  C25D5/02

CPC classification number: H01L24/11 ,  C23C14/34 ,  C25D5/02 ,  C25D7/12 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/03001 ,  H01L2224/0401 ,  H01L2224/11001 ,  H01L2924/01029 ,  H05K1/111 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0367 ,  Y10T29/49124

Abstract: A connection structure for a substrate is provided. The substrate has a plurality of connection pads and an insulation protection layer with the connection pads being exposed therefrom. The connection structure includes a metallic layer formed on an exposed surface of each of the connection pads and extending to the insulation protection layer, and a plurality of conductive bumps disposed on the metallic layer and spaced apart from one another at a distance less than or equal to 80 μm, each of conductive bumps having a width less than a width of each of the connection pads. Since the metallic layer covers the exposed surfaces of the connection pads completely, a colloid material will not flow to a surface of the connection pads during a subsequent underfilling process of a flip-chip process. Therefore, the colloid material will not be peeled off from the connection pads.

Abstract translation: 提供了一种用于基板的连接结构。 衬底具有多个连接焊盘和绝缘保护层，其中连接焊盘从其暴露。 连接结构包括形成在每个连接焊盘的暴露表面上并延伸到绝缘保护层的金属层，以及设置在金属层上并以小于或等于的距离彼此间隔开的多个导电凸块 每个导电凸块的宽度小于每个连接焊盘的宽度。 由于金属层完全覆盖连接焊盘的暴露表面，所以在随后的倒装芯片工艺的底部填充过程中，胶体材料将不会流到连接焊盘的表面。 因此，胶体材料不会从连接垫剥离。

公开(公告)号：US20140131072A1

公开(公告)日：2014-05-15

申请号：US13729710

申请日：2012-12-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chih-Sheng Lin ,  Chun-Lung Chen ,  Hsin-Hung Lee

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H01L24/11 ,  C23C14/34 ,  C25D5/02 ,  C25D7/12 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/03001 ,  H01L2224/0401 ,  H01L2224/11001 ,  H01L2924/01029 ,  H05K1/111 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0367 ,  Y10T29/49124

Abstract: A connection structure for a substrate is provided. The substrate has a plurality of connection pads and an insulation protection layer with the connection pads being exposed therefrom. The connection structure includes a metallic layer formed on an exposed surface of each of the connection pads and extending to the insulation protection layer, and a plurality of conductive bumps disposed on the metallic layer and spaced apart from one another at a distance less than or equal to 80 μm, each of conductive bumps having a width less than a width of each of the connection pads. Since the metallic layer covers the exposed surfaces of the connection pads completely, a colloid material will not flow to a surface of the connection pads during a subsequent underfilling process of a flip-chip process. Therefore, the colloid material will not be peeled off from the connection pads.

Abstract translation: 提供了一种用于基板的连接结构。 衬底具有多个连接焊盘和绝缘保护层，其中连接焊盘从其暴露。 连接结构包括形成在每个连接焊盘的暴露表面上并延伸到绝缘保护层的金属层，以及设置在金属层上并以小于或等于的距离彼此间隔开的多个导电凸块 每个导电凸块的宽度小于每个连接焊盘的宽度。 由于金属层完全覆盖连接焊盘的暴露表面，所以在随后的倒装芯片工艺的底部填充过程中，胶体材料将不会流到连接焊盘的表面。 因此，胶体材料不会从连接垫剥离。

公开(公告)号：US20140021591A1

公开(公告)日：2014-01-23

申请号：US13728112

申请日：2012-12-27

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Tse-Shih Sung ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L23/60

CPC classification number: H01L23/60 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor element is provided, including: a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference.

Abstract translation: 提供一种半导体元件，包括：具有形成在其中的多个第一导电通孔和第二导电通孔的基板; 形成在所述基板上并具有电连接到所述第一导电通孔的多个导电焊盘的再分布层; 以及形成在再分布层上并电连接到第二导电通孔的金属层。 金属层还具有多个开口，用于再分配层的导电焊盘从开口暴露而不电连接第一金属层。 因此，金属层和第二导电贯通孔形成能够防止电磁波进入或离开半导体元件的再分布层或侧面的屏蔽结构，从而有效地屏蔽电磁干扰。

公开(公告)号：US20140015621A1

公开(公告)日：2014-01-16

申请号：US13644507

申请日：2012-10-04

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Ming-Fan Tsai ,  Hsin-Hung Lee ,  Chia-Chu Lai ,  Yen-Yu Chen ,  Ho-Chuan Lin

IPC: H03H5/10

CPC classification number: H03H7/42

Abstract: A balanced-to-unbalanced converter (balun) is provided, including: a converting circuit having a first processing circuit including a first inductor and a first capacitor connected in series, a second processing circuit including a second capacitor and a second inductor connected in series, the second capacitor being electrically connected to the first inductor, and two balanced output ends connected to the first processing circuit and the second processing circuit, respectively; and a preprocessing circuit connected to the converting circuit and including an unbalanced input end for converting real impedance at the unbalanced input end into complex impedance at the balanced output ends. Accordingly, the balun satisfies the need of the wireless communication chips by providing differential signals with complex impedance. This is done by employing the preprocessing circuit in conjunction with the converting circuit to convert an unbalanced signal with real impedance into a balanced signal with complex impedance.

Abstract translation: 提供了一种平衡 - 不平衡转换器（balun），包括：具有第一处理电路的转换电路，包括第一电感器和串联连接的第一电容器，第二处理电路包括串联连接的第二电容器和第二电感器 所述第二电容器电连接到所述第一电感器，以及两个平衡输出端分别连接到所述第一处理电路和所述第二处理电路; 以及连接到转换电路并且包括用于将不平衡输入端处的实际阻抗转换成平衡输出端的复阻抗的不平衡输入端的预处理电路。 因此，平衡 - 不平衡变压器通过提供具有复阻抗的差分信号来满足无线通信芯片的需要。 这通过使用预处理电路与转换电路结合来实现，将具有实际阻抗的不平衡信号转换成具有复阻抗的平衡信号。

公开(公告)号：US09887102B2

公开(公告)日：2018-02-06

申请号：US15054845

申请日：2016-02-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tai-Tsung Hsu ,  Cheng-Yu Chiang ,  Miao-Wen Chen ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L21/56 ,  H01L23/36 ,  H01L23/552 ,  H01L23/31 ,  H01L21/428 ,  H01L23/367 ,  H01L23/58 ,  H01L25/065

CPC classification number: H01L21/56 ,  H01L21/428 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/552 ,  H01L23/585 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/1815

Abstract: A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided.

公开(公告)号：US20130277858A1

公开(公告)日：2013-10-24

申请号：US13628620

申请日：2012-09-27

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Tse-Shih Sung ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5225 ,  H01L23/64 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: An electrical interconnection structure includes: a signal transmission structure having a first through silicon via (TSV) and signal circuits connected to two opposite ends of the first TSV, respectively; and a grounding structure having a second TSV and grounding layers connected to two opposite ends of the second TSV, respectively. The grounding layers surround the signal circuits along the pathways thereof such that the ends of the first TSV are surrounded by the grounding layers with gaps therebetween. By changing the gaps between the grounding layers and the ends of the first TSV, the capacitance between the grounding layers and the signal circuits is adjusted so as to regulate the impedance therebetween.

Abstract translation: 电互连结构包括：信号传输结构，其具有分别连接到第一TSV的两个相对端的第一穿通硅通孔（TSV）和信号电路; 以及具有分别连接到第二TSV的两个相对端的第二TSV和接地层的接地结构。 接地层沿其路径围绕信号电路，使得第一TSV的端部被接地层包围，其间具有间隙。 通过改变接地层和第一TSV的端部之间的间隙，调整接地层和信号电路之间的电容，以便调节它们之间的阻抗。

公开(公告)号：US09305885B2

公开(公告)日：2016-04-05

申请号：US13960064

申请日：2013-08-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tai-Tsung Hsu ,  Cheng-Yu Chiang ,  Miao-Wen Chen ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L23/552 ,  H01L21/00 ,  H01L23/31 ,  H01L23/36 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/428 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/552 ,  H01L23/585 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/1815

Abstract: A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided.

Abstract translation: 提供一种多芯片封装结构，包括具有接地结构的基板; 两个半导体元件设置在基板上并与其电连接; 形成在所述基板上并封装半导体元件的密封剂，其中所述密封剂具有形成在所述半导体元件之间的多个圆形孔; 以及形成在每个圆孔中的电磁屏蔽结构，并连接到接地结构以实现电磁屏蔽效果。 还提供了一种用于形成多芯片封装的方法。