公开(公告)号：US20160141255A1

公开(公告)日：2016-05-19

申请号：US14824570

申请日：2015-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/54 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L23/147 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

Abstract translation: 提供了一种半导体封装，其包括：具有第一底表面和与第一底表面相对的第一顶表面的电路结构; 至少一个半导体元件，设置在电路结构的第一顶表面上并电连接到电路结构; 形成在所述电路结构的第一顶表面上以封装所述半导体元件的密封剂，其中所述密封剂具有面向所述电路结构的第一顶表面的第二底表面和与所述第二底表面相对的第二顶表面; 以及形成在密封剂的第二顶表面上或形成在电路结构和密封剂之间或形成在电路结构的第一底表面上的强化层，从而有效地防止密封剂翘曲并且半导体元件破裂。

公开(公告)号：US20180068959A1

公开(公告)日：2018-03-08

申请号：US15698136

申请日：2017-09-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/16 ,  H01L23/31 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/7684 ,  H01L23/147 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

公开(公告)号：US10811367B2

公开(公告)日：2020-10-20

申请号：US16360511

申请日：2019-03-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538 ,  H01L23/16 ,  H01L23/31 ,  H01L21/768

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

公开(公告)号：US20190287928A1

公开(公告)日：2019-09-19

申请号：US16360511

申请日：2019-03-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/16 ,  H01L23/31 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

公开(公告)号：US10340228B2

公开(公告)日：2019-07-02

申请号：US15698136

申请日：2017-09-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

公开(公告)号：US09786610B2

公开(公告)日：2017-10-10

申请号：US14824570

申请日：2015-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/16 ,  H01L23/31 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L23/147 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.