公开(公告)号：US20190273054A1

公开(公告)日：2019-09-05

申请号：US16295727

申请日：2019-03-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yi-Hsin Chen ,  Chia-Hsin Wu ,  Po-Yi Wu

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A substrate structure and a method for fabricating the same are provided. A barrier layer is formed on an entire top surface of a wiring layer of a substrate body to isolate the wiring layer from moisture and prevent the wiring layer from being oxidized. Therefore, the wiring layer is securely bonded to an insulation layer, thereby preventing the delamination or peeling problem from occurring.

公开(公告)号：US09903024B2

公开(公告)日：2018-02-27

申请号：US14688510

申请日：2015-04-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Yi Wu ,  Chun-Hung Lu

IPC: H05K1/11 ,  C23F1/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14

CPC classification number: C23F1/00 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/11 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

公开(公告)号：US20160141255A1

公开(公告)日：2016-05-19

申请号：US14824570

申请日：2015-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/54 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L23/147 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

Abstract translation: 提供了一种半导体封装，其包括：具有第一底表面和与第一底表面相对的第一顶表面的电路结构; 至少一个半导体元件，设置在电路结构的第一顶表面上并电连接到电路结构; 形成在所述电路结构的第一顶表面上以封装所述半导体元件的密封剂，其中所述密封剂具有面向所述电路结构的第一顶表面的第二底表面和与所述第二底表面相对的第二顶表面; 以及形成在密封剂的第二顶表面上或形成在电路结构和密封剂之间或形成在电路结构的第一底表面上的强化层，从而有效地防止密封剂翘曲并且半导体元件破裂。

公开(公告)号：US20180068959A1

公开(公告)日：2018-03-08

申请号：US15698136

申请日：2017-09-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/16 ,  H01L23/31 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/7684 ,  H01L23/147 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

公开(公告)号：US11913121B2

公开(公告)日：2024-02-27

申请号：US16991999

申请日：2020-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Yi Wu ,  Chun-Hung Lu

IPC: C23F1/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H05K3/10

CPC classification number: C23F1/00 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49827 ,  H05K3/108 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2224/11 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  Y10T29/49165 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

公开(公告)号：US20190287928A1

公开(公告)日：2019-09-19

申请号：US16360511

申请日：2019-03-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/16 ,  H01L23/31 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

公开(公告)号：US20160050753A1

公开(公告)日：2016-02-18

申请号：US14739026

申请日：2015-06-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Ching Chan ,  Chien-Min Lin ,  Po-Yi Wu ,  Chun-Hung Lu

IPC: H05K1/11 ,  H05K3/42 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H05K1/112 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/423 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method for fabricating an interposer is provided, which includes the steps of: providing a substrate body having opposite first and second sides and a plurality of conductive through holes communicating the first and second sides; forming an insulating layer on the first side of the substrate body, wherein the insulating layer has a plurality of openings correspondingly exposing the conductive through holes; and forming a plurality of conductive pads in the openings of the insulating layer, wherein the conductive pads are electrically connected to the corresponding conductive through holes, thereby dispensing with the conventional wet etching process and hence preventing an undercut structure from being formed under the conductive pads.

Abstract translation: 提供了一种用于制造插入件的方法，其包括以下步骤：提供具有相对的第一和第二侧面的基板本体和连通第一和第二侧面的多个导电通孔; 在所述基板主体的第一侧上形成绝缘层，其中所述绝缘层具有多个对应地暴露所述导电通孔的开口; 并且在绝缘层的开口中形成多个导电焊盘，其中导电焊盘电连接到相应的导电通孔，从而分配常规的湿蚀刻工艺，从而防止在导电焊盘下方形成底切结构 。

公开(公告)号：US20200370184A1

公开(公告)日：2020-11-26

申请号：US16991999

申请日：2020-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Yi Wu ,  Chun-Hung Lu

IPC: C23F1/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

公开(公告)号：US10811367B2

公开(公告)日：2020-10-20

申请号：US16360511

申请日：2019-03-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538 ,  H01L23/16 ,  H01L23/31 ,  H01L21/768

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

公开(公告)号：US10192838B2

公开(公告)日：2019-01-29

申请号：US15411204

申请日：2017-01-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Lung Chuang ,  Po-Yi Wu ,  Meng-Tsung Lee ,  Yih-Jenn Jiang

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/31

Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.