公开(公告)号：US20230216518A1

公开(公告)日：2023-07-06

申请号：US18182128

申请日：2023-03-10

Applicant: Socionext Inc.

Inventor： Itsuki YOSHIDA ,  Takashi MORIE

IPC: H03M1/36 ,  H03K19/21

CPC classification number: H03M1/36 ,  H03K19/21

Abstract: A comparator circuit outputs first and second digital signals corresponding to differential signals to a flip-flop having a predetermined forbidden input combination. A converter circuit performs differential amplification for the differential signals and converts the resultant signals to first and second signals that are complementary digital signals. A logic circuit performs predetermined logical operation, and when the logical values of the first and second signals are different from each other, outputs the first and second digital signals corresponding to the logical values of the first and second signals, and when the logical values of the first and second signals are the same, outputs the first and second digital signals having a same value other than the predetermined forbidden input combination.