公开(公告)号：US20190068213A1

公开(公告)日：2019-02-28

申请号：US16157741

申请日：2018-10-11

Applicant: SOCIONEXT INC.

Inventor： Daisuke NOMASAKI ,  Takashi MORIE

IPC: H03M1/38 ,  G05F3/16

Abstract: A transistor (M1) whose gate is capacitance-coupled to a wiring (L1) is connected between the wirings (L1, L2) connected to output nodes (OT1, OT2) outputting a reference voltage (VREF_OUT). A replica circuit (20) having a resistor (22) and a transistor (M2) connected in series is provided between the wirings (L1, L2). Gates of the transistors (M1, M2) are connected to each other. A differential amplifier (23) receives a voltage (V_RP) of a node (N1) between the resistor (22) and the transistor (M1) and a standard voltage (V_ID), and provides an output to the gate of the transistor (M2).

公开(公告)号：US20230216518A1

公开(公告)日：2023-07-06

申请号：US18182128

申请日：2023-03-10

Applicant: Socionext Inc.

Inventor： Itsuki YOSHIDA ,  Takashi MORIE

IPC: H03M1/36 ,  H03K19/21

CPC classification number: H03M1/36 ,  H03K19/21

Abstract: A comparator circuit outputs first and second digital signals corresponding to differential signals to a flip-flop having a predetermined forbidden input combination. A converter circuit performs differential amplification for the differential signals and converts the resultant signals to first and second signals that are complementary digital signals. A logic circuit performs predetermined logical operation, and when the logical values of the first and second signals are different from each other, outputs the first and second digital signals corresponding to the logical values of the first and second signals, and when the logical values of the first and second signals are the same, outputs the first and second digital signals having a same value other than the predetermined forbidden input combination.

公开(公告)号：US20160308553A1

公开(公告)日：2016-10-20

申请号：US15194420

申请日：2016-06-27

Applicant: SOCIONEXT INC.

Inventor： Yosuke MITANI ,  Takashi MORIE ,  Kazuo MATSUKAWA

IPC: H03M3/00 ,  H04B3/54 ,  H04B14/06

CPC classification number: H03M3/422 ,  H03M3/458 ,  H03M3/48 ,  H04B3/542 ,  H04B14/06

Abstract: Disclosed herein is an integrator including: a resistive element connected to an input terminal; an operational amplifier configured to receive, through the resistive element, an input signal that has been supplied to the input terminal; and a voltage regulator circuit connected to an intermediate node between the resistive element and the operational amplifier. The voltage regulator circuit has a first current source connected to the intermediate node, and a switch connected between the intermediate node and the first current source and selectively turning ON or OFF.

Abstract translation: 这里公开了一种积分器，包括：连接到输入端子的电阻元件; 运算放大器，被配置为通过电阻元件接收已经提供给输入端的输入信号; 以及连接到电阻元件和运算放大器之间的中间节点的电压调节器电路。 电压调节器电路具有连接到中间节点的第一电流源和连接在中间节点和第一电流源之间并且选择性地导通或关断的开关。