公开(公告)号：US20200243128A1

公开(公告)日：2020-07-30

申请号：US16847551

申请日：2020-04-13

Applicant: Socionext Inc.

Inventor： Masataka Sato ,  Hideo Akiyoshi ,  Masanobu Hirose ,  Yoshinobu Yamagami

IPC: G11C11/408 ,  G11C11/4099 ,  G11C5/02

Abstract: First and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.

公开(公告)号：US10943643B2

公开(公告)日：2021-03-09

申请号：US16847551

申请日：2020-04-13

Applicant: SOCIONEXT INC.

Inventor： Masataka Sato ,  Hideo Akiyoshi ,  Masanobu Hirose ,  Yoshinobu Yamagami

IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4099

Abstract: First and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.