公开(公告)号：US07483032B1

公开(公告)日：2009-01-27

申请号：US11253438

申请日：2005-10-18

申请人： Sonny S. Yeoh ,  Shane J. Keil ,  Dennis K. Ma ,  Peter C. Tong

发明人： Sonny S. Yeoh ,  Shane J. Keil ,  Dennis K. Ma ,  Peter C. Tong

IPC分类号： G06F12/00 ,  G06F15/16 ,  G06F12/08

CPC分类号： G09G5/363

摘要： Circuits, methods, and apparatus that allow the elimination of a frame buffer connected directly to a graphics processing unit. The graphics processing unit includes an on-chip memory. Following system power-up or reset, the GPU initially renders comparatively low-resolution images to the on-chip memory for display. Afterward, the GPU renders images, which are typically higher resolution, and stores them in a system memory, apart from the graphics processing unit. The on-chip memory, which is no longer needed for image storage, instead stores address information, referred to as page tables, identifying the location of data stored by the GPU in the separate system memory.

摘要翻译： 允许消除直接连接到图形处理单元的帧缓冲器的电路，方法和装置。 图形处理单元包括片上存储器。 在系统上电或复位后，GPU最初将相对较低分辨率的图像呈现给片上存储器进行显示。 之后，GPU将呈现通常较高分辨率的图像，并将它们存储在除了图形处理单元之外的系统存储器中。 不再需要用于图像存储的片上存储器，而是存储称为页表的地址信息，其将GPU存储的数据的位置识别在单独的系统存储器中。

公开(公告)号：US20080028181A1

公开(公告)日：2008-01-31

申请号：US11689485

申请日：2007-03-21

申请人： Peter C. Tong ,  Sonny S. Yeoh ,  Kevin J. Kranzusch ,  Gary D. Lorensen ,  Kaymann L. Woo ,  Ashish Kishen Kaul ,  Colyn S. Case ,  Stefan A. Gottschalk ,  Dennis K. Ma

发明人： Peter C. Tong ,  Sonny S. Yeoh ,  Kevin J. Kranzusch ,  Gary D. Lorensen ,  Kaymann L. Woo ,  Ashish Kishen Kaul ,  Colyn S. Case ,  Stefan A. Gottschalk ,  Dennis K. Ma

IPC分类号： G06F12/00

CPC分类号： G06F3/14 ,  G06F12/1027 ,  G06F2212/654 ,  G06T1/60 ,  G09G5/36 ,  G09G5/363 ,  G09G2330/026 ,  G09G2360/121 ,  G09G2360/125

摘要： Circuits, methods, and apparatus that reduce or eliminate system memory accesses to retrieve address translation information. In one example, these accesses are reduced or eliminated by pre-populating a graphics TLB with entries that are used to translate virtual addresses used by a GPU to physical addresses used by a system memory. Translation information is maintained by locking or restricting entries in the graphics TLB that are needed for display access. This may be done by limiting access to certain locations in the graphics TLB, by storing flags or other identifying information in the graphics TLB, or by other appropriate methods. In another example, memory space is allocated by a system BIOS for a GPU, which stores a base address and address range. Virtual addresses in the address range are translated by adding them to the base address.

摘要翻译： 减少或消除系统存储器访问以检索地址转换信息的电路，方法和装置。 在一个示例中，通过用用于将GPU使用的虚拟地址转换为系统存储器使用的物理地址的条目预先填充图形TLB来减少或消除这些访问。 通过锁定或限制显示访问所需的图形TLB中的条目来维护翻译信息。 这可以通过在图形TLB中限制对图形TLB中的某些位置的访问，通过在图形TLB中存储标志或其他识别信息，或通过其他适当的方法来实现。 在另一示例中，内存空间由用于存储基地址和地址范围的GPU的系统BIOS分配。 将地址范围中的虚拟地址添加到基地址中。

公开(公告)号：US07415575B1

公开(公告)日：2008-08-19

申请号：US11298256

申请日：2005-12-08

申请人： Peter C. Tong ,  Colyn S. Case

发明人： Peter C. Tong ,  Colyn S. Case

IPC分类号： G06F12/12

CPC分类号： G06F12/122 ,  G06F12/126

摘要： A cache shared by multiple clients implements a client specific policy for replacing entries in the event of a cache miss. A request from any client can hit any entry in the cache. For purposes of replacing entries, at least of the clients is restricted, and when a cache miss results from a request by the restricted client, the entry to be replaced is selected from a fixed subset of the cache entries. When a cache misses results from a request by any client other than the restricted client, any cache entry, including a restricted entry, can be selected to be replaced.

摘要翻译： 多个客户端共享的缓存实现了客户端特定的策略，用于在高速缓存未命中的情况下替换条目。 来自任何客户端的请求可以访问缓存中的任何条目。 为了替换条目，至少客户端被限制，并且当由受限客户端的请求导致高速缓存未命中时，从缓存条目的固定子集中选择要替换的条目。 当缓存从除受限客户端之外的任何客户端的请求中忽略结果时，可以选择任何高速缓存条目（包括受限条目）进行替换。

公开(公告)号：US5581473A

公开(公告)日：1996-12-03

申请号：US605800

申请日：1996-02-23

申请人： Stefan Rusu ,  Stuart A. Taylor ,  Peter C. Tong ,  Gregory Schulte

发明人： Stefan Rusu ,  Stuart A. Taylor ,  Peter C. Tong ,  Gregory Schulte

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  Y10S707/99931

摘要： A repository, a loader, a model generator, a constraint generator, and a number of timing analysis tools, are provided for managing timing requirement specifications and measurements, and generating timing models and constraints of a VLSI circuit. The repository stores the timing specifications and measurements for each pin instances and each flow through arc instances. Timing specifications and measurements are identified by their classes including at least one current specification class and at least one measurement class for one timing analysis tool. Additionally, the repository stores a number of characteristics for each pin instance, the pin compositions of each net, and the hierarchical relationship of the functional block instances. The loader loads the various information into the repository. The timing model generator generates the timing models for the various functional blocks, using the stored information in the repository. The timing constraint generator in cooperation with the timing model generator and at least one timing analysis tool generates the timing constraints for the various functional block instances, using the stored information in the repository, the generated timing models of the functional blocks, and a number of timing analysis scripts.

摘要翻译： 提供存储库，加载器，模型生成器，约束生成器和多个时序分析工具，用于管理定时需求规范和测量，以及生成VLSI电路的定时模型和约束。 存储库存储每个针脚实例的时序规格和测量值，每个流程通过圆弧实例。 定时规范和测量由其类别标识，包括至少一个当前规范类别和至少一个测量类别，用于一个时序分析工具。 另外，存储库存储每个引脚实例的多个特性，每个网络的引脚组成以及功能块实例的分层关系。 加载器将各种信息加载到存储库中。 定时模型生成器使用存储库中存储的信息生成各种功能块的时序模型。 与定时模型发生器和至少一个定时分析工具协作的时序约束生成器使用存储库中存储的信息，生成的功能块的定时模型和多个功能块的时间模型来生成各种功能块实例的时序约束 时序分析脚本。